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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 5/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
TABLE OF CONTENTS
MOTOROLA
v
Paragraph
Title
Page
SECTION 1 OVERVIEW
1.1
1.2
1.3
Block Diagram ...........................................................................................1-1
QADC Features .........................................................................................1-2
Memory Map .............................................................................................1-2
SECTION 2 SIGNAL DESCRIPTIONS
2.1
2.1.1
2.1.2
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Port A Pin Functions ..................................................................................2-2
Port A Analog Input Pins ...................................................................2-2
Port A Digital Input/Output Pins .........................................................2-2
Port B Pin Functions ..................................................................................2-2
Port B Analog Input Pins ...................................................................2-2
Port B Digital Input Pins ....................................................................2-2
External Trigger Input Pins ........................................................................2-3
Multiplexed Address Output Pins ..............................................................2-3
Multiplexed Analog Input Pins ...................................................................2-3
Voltage Reference Pins .............................................................................2-4
Dedicated Analog Supply Pins ..................................................................2-4
External Digital Supply Pin ........................................................................2-4
Internal Digital Supply Pins .......................................................................2-4
SECTION 3 CONFIGURATION AND CONTROL
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
3.5.1
3.5.2
QADC Bus Interface Unit ..........................................................................3-1
QADC Bus Accessing ...............................................................................3-1
Module Configuration ................................................................................3-3
Low Power Stop Mode ......................................................................3-3
Freeze Mode .....................................................................................3-4
Supervisor/Unrestricted Address Space ...........................................3-4
Interrupt Arbitration Priority ...............................................................3-5
QADC Module Configuration Register ..............................................3-5
QADC Test Register ..................................................................................3-6
General-Purpose I/O Port Operation .........................................................3-6
Port Data Register .............................................................................3-6
Port Data Direction Register ..............................................................3-7
SECTION 4 EXTERNAL MULTIPLEXING
4.1
4.2
External Multiplexing Operation ................................................................4-1
Module Version Options ............................................................................4-3
TABLE OF CONTENTS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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