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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 44/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
6-2
ANALOG SUBSYSTEM
QADC
REFERENCE MANUAL
6.1.1 Conversion Cycle Times
Total conversion time is made up of initial sample time, transfer time, final sample time,
and resolution time. Initial sample time refers to the time during which the selected in-
put channel is connected to the sample capacitor at the input of the sample buffer am-
plifier. During the transfer period, the sample capacitor is disconnected from the
multiplexer, and the stored voltage is buffered and transferred to the RC DAC array.
During the final sampling period, the sample capacitor and amplifier are bypassed,
and the multiplexer input charges the RC DAC array directly. During the resolution pe-
riod, the voltage in the RC DAC array is converted to a digital value and stored in the
SAR.
Initial sample time is fixed at two QCLKs and the transfer time at four QCLKs. Final
sample time can be 2, 4, 8, or 16 ADC clock cycles, depending on the value of the IST
field in the CCW. Resolution time is ten cycles.
Transfer and resolution require a minimum of 18 QCLK clocks (8.6
μ
s with a 2.1-MHz
QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total
conversion time is 15.2
μ
s (with a 2.1-MHz QCLK).
Figure 6-2
illustrates the timing for conversions. This diagram assumes a final sam-
pling period of two QCLKs.
Figure 6-2 Conversion Timing
6.1.1.1 Amplifier Bypass Mode Conversion Timing
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass
(BYP) field in the CCW, the timing changes to that shown in
Figure 6-3
. Refer to para-
graph 7.7 in
SECTION 7 DIGITAL CONTROL
for more information on the BYP field.
The initial sample time and the transfer time are eliminated reducing the potential con-
version time by six QCLKs. However, due to internal RC effects, a minimum final sam-
INITIAL
SAMPLE
TIME
2 CYCLES
TRANSFER
TIME
4 CYCLES
FINAL SAMPLE
TIME
N CYCLES:
(2, 4, 8, 16)
RESOLUTION
TIME
10 CYCLES
SAMPLE AND TRANSFER
TIME
SUCCESSIVE APPROXIMATION RESOLUTION
SEQUENCE
QCLK
QADC CONVERSION TIM
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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