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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 26/122頁(yè) |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
3-6
CONFIGURATION AND CONTROL
QADC
REFERENCE MANUAL
IARB[3:0] — Interrupt Arbitration Number
IARB determines QADC interrupt arbitration priority. An IARB field can be assigned a
value from %0001 (lowest priority) to %1111 (highest value). Refer to
SECTION 8 IN-
TERRUPTS
for more information.
3.4 QADC Test Register
QADCTEST —
QADC Test Register
QADCTEST is used only during factory testing of the MCU.
$####02
3.5 General-Purpose I/O Port Operation
Each of the port pins, when used as a general-purpose input, is conditioned by a syn-
chronizer with an enable feature. The synchronizer is not enabled until the QADC de-
codes an IMB bus cycle which addresses the port data register to minimize the high-
current effect of mid-level signals on the inputs used for analog signals. Digital input
signals must meet the input low voltage (V
IL
) or input high voltage (V
IH
) specifications
in
APPENDIX A ELECTRICAL CHARACTERISTICS
. If an analog input pin does not
meet the digital input pin specifications when a digital port read operation occurs, an
indeterminate state is read.
During a port data register read, the actual value of the pin is reported when its corre-
sponding bit in the data direction register defines the pin to be an input (port A only).
When the data direction bit specifies the pin to be an output, the content of the port
data register is read. By reading the latch which drives the output pin, software instruc-
tions that read data, modify it, and write the result, like bit manipulation instructions,
work correctly. When a reduced number of digital port pins are implemented on a par-
ticular microcontroller version, the unused bit positions are read as a zero and write
operations do not have any effect.
There are two special cases to consider for the digital I/O port operation. When the
MUX (externally multiplexed) bit is set in QACR0, the data direction register settings
are ignored for the bits corresponding to PQA[2:0], the three multiplexed address
(MA[2:0]) output pins. The MA[2:0] pins are forced to be digital outputs, regardless of
the data direction setting, and the multiplexed address outputs are driven. The data
returned during a port data register read is the value of the multiplexed address latches
which drive MA[2:0], regardless of the data direction setting.
Similarly, when an external trigger queue operating mode is selected, the data direc-
tion setting for the corresponding pins, PQA3 or PQA4, is ignored. The port pins are
forced to be digital inputs for ETRIG1 and/or ETRIG2. The data driven during a port
data register read is the actual value of the pin, regardless of the data direction setting.
3.5.1 Port Data Register
QADC ports A and B are accessed through two 8-bit port data registers (PORTQA and
PORTQB).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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