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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 24/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
3-4
CONFIGURATION AND CONTROL
QADC
REFERENCE MANUAL
3.3.2 Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the device inte-
gration module and a breakpoint is encountered. This is indicated by the assertion of
the internal FREEZE line on the IMB. The FRZ bit in the QADCMCR determines
whether or not the QADC responds to an IMB internal FREEZE signal assertion.
Freeze is very useful when debugging an application.
When the FRZ bit is set, the QADC finishes any current conversion then freezes. De-
pending on when the FRZ bit is asserted, there are three possible queue “freeze” sce-
narios:
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current conversion and
then freezes.
If during the execution of the current conversion, the queue operating mode for
the active queue is changed, or a queue 2 abort occurs, the QADC freezes im-
mediately.
When the QADC enters the freeze mode while a queue is active, the current CCW lo-
cation of the queue pointer is saved.
During freeze, the analog clock is held in reset and is not clocked. Although QCLK is
unaffected, the periodic/interval timer is held in reset. External trigger events that oc-
cur during the freeze mode are not recorded. The BIU remains active to allow IMB ac-
cess to all QADC registers and RAM. Although the QADC saves a pointer to the next
CCW in the current queue, the software can force the QADC to execute a different
CCW by writing new queue operating modes for normal operation. The QADC looks
at the queue operating modes, the current queue pointer, and any pending trigger
events to decide which CCW to execute.
If the FRZ bit is clear, the internal FREEZE signal is ignored.
3.3.3 Supervisor/Unrestricted Address Space
The QADC memory map is divided into two segments: supervisor-only data space and
assignable data space. Access to supervisor-only data space is permitted only when
the software is operating in supervisor access mode. Assignable data space can be
either restricted to supervisor-only access or unrestricted to both supervisor and user
data space accesses. The SUPV bit in the QADCMCR designates the assignable
space as supervisor or unrestricted.
Attempts to read a supervisor-only data space when not in the supervisor access
mode causes a value of $0000 to be returned. Attempts to read assignable data space
in the unrestricted access mode when the space is programmed as supervisor space
causes a value of $FFFF to be returned. Attempts to write supervisor-only or supervi-
sor-assigned data space when in the unrestricted access mode has no effect.
The CPU indicates the supervisor and user space access with the function code bits
(FC[2:0]) on the IMB bus.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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