參數(shù)資料
型號(hào)： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè)
文件頁(yè)數(shù)： 14/122頁(yè)
文件大小： 940K
代理商： QADCRM
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MOTOROLA
1-2
OVERVIEW
QADC
REFERENCE MANUAL
The bus interface unit (BIU) allows the QADC to operate with the applications software
through the IMB environment.
1.2 QADC Features
Sample and hold
Up to 16 analog input channels using internal multiplexing
Directly supports up to four external multiplexers (for example, the MC14051)
Up to 44 total input channels with internal and external multiplexing
Programmable input sample time for various source impedances
Two conversion command queues of variable length
Sub-queues possible using pause mechanism
Queue complete and pause software interrupts available on both queues
Automated queue modes initiated by:
— External trigger
— Periodic/interval timer, within QADC module
— Software command
Single-scan or continuous-scan of queues
40 result registers
Output data readable in three formats:
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
Unused analog channels can be used as digital ports
1.3 Memory Map
The QADC occupies 512 bytes, or 256 words, of address space. Nine words are con-
trol, port, and status registers, 40 words are the CCW table, and 40 words are the re-
sult word table which occupy 120 address locations because the result data is
readable in three data alignment formats. The remaining words are reserved for ex-
pansion.
Table 1-1
displays the QADC memory map.
Each register address in
The offset represents the nine low order bits of register address. “$####” represents
the 15-bit base address plus the high order bit of the offset. (For example, both LJUR
and RJUR registers are represented by $####B0–$####FE, even though they repre-
sent different addresses since each register has a different most significant bit in their
offset). For the precise locations of these registers, refer to the appropriate microcon-
troller unit (MCU) manual. The column labeled “Access” specifies which address
space is designated supervisor data space or unrestricted data space. Remember that
the MSB is determined by the MM bit.
Table 1-1
consists of a 15-bit base address plus a 9-bit offset.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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