參數(shù)資料
型號(hào)： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè)
文件頁(yè)數(shù)： 3/122頁(yè)
文件大小： 940K
代理商： QADCRM
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QADC
REFERENCE MANUAL
PREFACE
MOTOROLA
iii
PREFACE
This manual describes the capabilities, operation, and functions of the queued analog-
to-digital converter (QADC). The following conventions are used throughout the man-
ual.
Logic level one
is the voltage that corresponds to Boolean true (1) state.
Logic level zero
is the voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one on the bit or bits.
To
clear
a bit or bits means to establish logic level zero on the bit or bits.
A signal that is
logic level one to logic level zero when asserted, and an active high signal changes
from logic level zero to logic level one.
asserted
is in its active logic state. An active low signal changes from
A signal that is
logic level zero to logic level one when negated, and an active high signal changes
from logic level one to logic level zero.
negated
is in its inactive logic state. An active low signal changes from
LSB
ences to low and high bytes are spelled out.
means least significant bit or bits.
MSB
means most significant bit or bits. Refer-
A
example, ADDR15 is bit 15 of the address bus.
to by mnemonic and the numbers that define the range. For example, DATA[7:0] form
the low byte of the data bus.
specific bit or signal
within a range is referred to by mnemonic and number. For
A range of bits or signals
is referred
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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