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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉換器參考手冊 |
| 文件頁數(shù)： | 21/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-1
SECTION 3 CONFIGURATION AND CONTROL
The QADC module communicates with other microcontroller modules via the inter-
module bus (IMB). The QADC bus interface unit (BIU) coordinates IMB activity with
internal QADC bus activity. This section describes the operation of the BIU, IMB read/
write accesses to QADC memory locations, module configuration, and general-pur-
pose I/O operation.
3.1 QADC Bus Interface Unit
The BIU is designed to act as a slave device on the IMB. The BIU has the following
functions: to respond with the appropriate bus cycle termination, and to supply IMB in-
terface timing to all internal module signals.
BIU components consist of IMB buffers, address match and module select logic, inter-
rupt and arbitration logic, the BIU state machine, clock prescaler logic, data bus routing
logic, and the interface to the internal module data bus.
The QADC responds to all IMB operations and signals, allowing byte, word, and long
word addressable read and write operations in any addressable space.
NOTE
Normal accesses to the QADC require two clocks. However, if the
CPU tries to access locations that are also accessible by the QADC
while the QADC is accessing them, the QADC produces wait states.
From one to four CPU wait states may be inserted by the QADC in
the process of reading and writing.
3.2 QADC Bus Accessing
The QADC permits software access to 8-bit, 16-bit words, and 32-bit long words, at
even and odd addresses, however, coherency (ensuring that all samples are taken
consecutively in one scan) is not provided for accesses that require more than one bus
cycle. For example, if a read of two consecutive word locations in a result area are
made, the QADC could change one word in the result area between the bus cycles.
There is no holding register for the second word. Refer to paragraph 7.6.3 in
SECTION
7 DIGITAL CONTROL
for more information on coherency. All read and write accesses
that require more than one 16-bit access to complete occur as two or more indepen-
dent bus cycles. These accesses include misaligned and long word accesses.
NOTE
CPU32 does not support word access or long word access to an odd
address. Both of these are considered misaligned accesses. The
CPU16 supports misaligned and long word accesses.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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