參數(shù)資料
型號(hào)： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè)
文件頁(yè)數(shù)： 41/122頁(yè)
文件大?。?/td> 940K
代理商： QADCRM
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QADC
REFERENCE MANUAL
PIN CONNECTION CONSIDERATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-9
capacitor array (C
DAC
) before each sample. The value of this supply is V
DDA
/2, or 2.5
volts for 5-volt operation.
The following paragraphs provide a simplified description of the interaction between
the QADC and the user's external circuitry. This circuitry is assumed to be a simple RC
low-pass filter passing a signal from a source to the QADC input pin. The following
simplifying assumptions are made:
The source impedance is included with the series resistor of the RC filter.
The external capacitor is perfect (no leakage, no significant dielectric absorption
characteristics, etc.)
All parasitic capacitance associated with the input pin is included in the value of
the external capacitor.
Inductance is ignored.
The "on" resistance of the internal switches is zero ohms and the "off" resistance
is infinite.
5.6.1 Settling Time for the External Circuit
The values for R
F
and C
F
in the user's external circuitry determine the length of time
required to charge C
F
to the source voltage level (V
SRC
). At time t = 0, S1 in
Figure 5-
7
closes. S2 is open, disconnecting the internal circuitry from the external circuitry. As-
sume that the initial voltage across C
F
is zero. As C
F
charges, the voltage across it is
determined by the following equation, where t is the total charge time:
When t = 0, the voltage across C
F
= 0. As t approaches infinity, V
CF
will equal V
SRC
.
(This assumes no internal leakage.) With 10-bit resolution, 1/2 of a count is equal to
1/2048 full-scale value. Assuming worst case (V
SRC
= full scale),
Table 5-1
shows the
required time for C
F
to charge to within 1/2 of a count of the actual source voltage dur-
ing 10-bit conversions.
Table 5-1
is based on the RC network in
Figure 5-7
.
NOTE
The following times are completely independent of the A/D converter
architecture (assuming the QADC is not affecting the charging).
Table 5-1 External Circuit Settling Time (10-Bit Conversions)
Filter Capacitor
(CF)
1
μ
F
.1
μ
F
.01
μ
F
.001
μ
F
100 pF
Source Resistance (R
F
)
1 k
7.6 ms
760
μ
s
76
μ
s
7.6
μ
s
760 ns
100
760
μ
s
76
μ
s
7.6
μ
s
760 ns
76 ns
10 k
76 ms
7.6 ms
760
μ
s
76
μ
s
7.6
μ
s
100 k
760 ms
76 ms
7.6 ms
760
μ
s
76
μ
s
V
CF
V
SRC
1
e
–
t
–
R
F
C
F
(
)
=
F
Freescale Semiconductor, Inc.
n
.
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