參數(shù)資料
型號: QADCRM
英文描述: Queued Analog-to-Digital Converter Reference Manual
中文描述: 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊
文件頁數(shù): 13/122頁
文件大小: 940K
代理商: QADCRM
QADC
REFERENCE MANUAL
OVERVIEW
MOTOROLA
1-1
SECTION 1 OVERVIEW
The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive ap-
proximation converter. A maximum of 16 analog input channels can be supported us-
ing internal multiplexing. A maximum of 44 input channels can be supported in the
expanded, externally multiplexed mode. The actual number of channels depends
upon the number of pins available to the QADC module.
1.1 Block Diagram
Figure 1-1
of an analog front-end and a digital control subsystem, which includes an intermodule
bus (IMB) interface block.
displays the major components of the QADC module. The QADC consists
Figure 1-1 QADC Block Diagram
The analog section includes input pins, an analog multiplexer, and two sample and
hold analog circuits. The analog conversion is performed by the digital-to-analog con-
verter (DAC) resistor-capacitor array and a high-gain comparator.
The digital control section contains control logic to sequence the conversion process,
channel select logic, and a successive approximation register (SAR). Also included
are the periodic/interval timer, control and status registers, the conversion command
word (CCW) table RAM, and the result word table RAM.
QADC BLOCK
QUEUE OF 10-BIT CONVERSION
COMMAND WORDS (CCW), 40 WORDS
INTERMODULE BUS
INTERFACE
DIGITAL
CONTROL
10-BIT RESULT TABLE,
40 WORDS
10-BIT TO 16-BIT
RESULT ALIGNMENT
10-BIT ANALOG TO DIGITAL CONVERTER
ANALOG INPUT MULTIPLEXER AND
DIGITAL PIN FUNCTIONS
EXTERNAL
TRIGGERS
EXTERNAL
MUX ADDRESS
UP TO 16 ANALOG
INPUT PINS
REFERENCE
INPUTS
ANALOG POWER
INPUTS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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