- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361246 > QADCRM Queued Analog-to-Digital Converter Reference Manual PDF資料下載
參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 22/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
MOTOROLA
3-2
CONFIGURATION AND CONTROL
QADC
REFERENCE MANUAL
Figure 3-1
shows the three bus cycles which are implemented by the QADC. The fol-
lowing paragraphs describe how the three types of accesses are used, including mis-
aligned and long word accesses.
Figure 3-1 Bus Cycle Accesses
Byte accesses to an even address read or write bits 15 through 8 of a QADC location,
as shown in the top illustration of
Figure 3-1
. In the case of write cycles, bits 7 through
0 of the addressed QADC register are not disturbed. In the case of read cycles, the
QADC provides zeros to the IMB for bits 7 through 0.
Byte accesses to an odd address read or write bits 7 through 0 of a QADC location,
as shown in the center illustration of
Figure 3-1
. In the case of write cycles, bits 15
through 8 of the addressed QADC location are not disturbed. In the case of read cy-
cles, the QADC provides zeros to the IMB for bits 15 through 8.
Word accesses to an even address read or write bits 15 through 0 of a QADC location,
as shown in the lower illustration of
Figure 3-1
. A full 16 bits of data is written to and
read from the QADC location with each access.
QADC BUS CYC ACC
00
INTERMODULE BUS
8-BIT ACCESS OF AN EVEN ADDRESS (ISIZ = 01, A0 = 0)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
INTERMODULE BUS
8-BIT ACCESS OF AN ODD ADDRESS (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
INTERMODULE BUS
16-BIT ALIGNED ACCESS (ISIZ = 10, A0 = 0)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
00
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QAK2E104JCP | PLASTIC FILM CAPACITORS |
| QAK2E104JTP | PLASTIC FILM CAPACITORS |
| QAK2E104KCP | PLASTIC FILM CAPACITORS |
| QAK2E104KTP | PLASTIC FILM CAPACITORS |
| QAK2E105JCP | PLASTIC FILM CAPACITORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QAE100 | 制造商:P-DUKE 制造商全稱:Power Mate Technology Co., LTD 功能描述:QUARTER-BRICK DC-DC CONVERTER 2:1 ULTRA WIDE INPUT RANGE UP TO 108Watts |
| QAE100W | 制造商:P-DUKE 制造商全稱:Power Mate Technology Co., LTD 功能描述:QUARTER-BRICK DC-DC CONVERTER 4:1 ULTRA WIDE INPUT RANGE UP TO 90Watts |
| QAE150 | 制造商:P-DUKE 制造商全稱:Power Mate Technology Co., LTD 功能描述:QUARTER-BRICK DC-DC CONVERTER 2:1 ULTRA WIDE INPUT RANGE UP TO 150Watts |
| QAE150W | 制造商:P-DUKE 制造商全稱:Power Mate Technology Co., LTD 功能描述:QUARTER-BRICK DC-DC CONVERTER 4:1 ULTRA WIDE INPUT RANGE UP TO 132Watts |
| QAEP | 制造商:Omnimount 功能描述:10.6 ~ 21 Inch Adjustable 1.5 Inch NPT Pipe Extension |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。