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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 59/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
DIGITAL CONTROL
MOTOROLA
7-13
Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS
for information on mini-
mum QCLK high time (T
PSH
) and the minimum QCLK low time (T
PSL
).
In order to be able to tune the QCLK as close as possible to the fastest conversion
time for any given system clock frequency, the QADC permits one more programma-
ble control of the QCLK high and low time. The PSA parameter in QACR0 allows the
QCLK high phase to be stretched for a half cycle of the system clock, and correspond-
ingly, the QCLK low phase is shortened by a half cycle of the system clock.
Example 2 in
Figure 7-3
is the same as Example 1, except that the PSA bit is set. The
QCLK high phase has 4.5 system clock cycles; the QCLK low phase has 3.5 system
clock cycles.
The following are equations for calculating the QCLK high and low phases:
High QCLK Time = 1000 (PSH + 1 + 0.5 PSA)
÷
F
SYS
(in ns)
Low QCLK Time = 1000 (PSL + 1 – 0.5 PSA)
÷
F
SYS
(in ns)
F
QCLK
= 1000
÷
(High QCLK Time + Low QCLK Time) (in MHz)
Where:
PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
PSA = 0 to 1, the prescaler QCLK add half cycle in QACR0
F
SYS
= System clock frequency in MHz
F
QCLK
= QCLK frequency in MHz
7.5 Periodic/Interval Timer
The on-chip periodic/interval timer is enabled to generate trigger events at a program-
mable interval, initiating execution of queue 2. The periodic/interval timer stays reset
under the following conditions:
Queue 2 is programmed to any queue operating mode which does not use the
periodic/interval timer
Interval timer single-scan mode is selected, but the single-scan enable bit is set
to zero
IMB system reset or the master reset is asserted
Stop mode is selected
Freeze mode is selected
Two other conditions which cause a pulsed reset of the timer are:
Roll over of the timer counter
A queue operating mode change from one periodic/interval timer mode to another
periodic/interval timer mode
During the stop mode, the periodic/interval timer is held in reset. Since stop mode
causes QACR2 to be initialized to zero, a valid periodic or interval timer mode must be
written to QACR2 after stop mode is exited to release the timer from reset.
When the IMB internal FREEZE line is asserted and a periodic or interval timer mode
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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