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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 6/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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6
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Packet Memory Interface
PIN#
46-43,
40,
38-35,
33-31,
29-25
46
Pin Name
MA[19:3]
Type
O,4ma
Description
Memory Address Bits 19-3:
MA19(RXD0)
I/O, 4ma
Memory Address Bit19, when on-chip tranceiver is used,
it is defined as MA19,while in MII mode, it is used as receive
data bit RXD0 pin.
Memory Address Bit18, when on-chip tranceiver is used,
it is defined as MA18,while in MII mode, it is used as receive
data bit RXD1 pin.
Memory Address Bit17, when on-chip tranceiver is used,
it is defined as MA17,while in MII mode, it is used as receive
data bit RXD2 pin.
Memory Address Bit16, when on-chip tranceiver is used,
it is defined as MA16,while in MII mode, it is used as receive
data bit RXD3 pin.
Memory Address Bit 2 or EEPROM Data Out bit: Right after the
host reset, GMAC automatically load the configuration informa-
tion from the external EEPROM. During this period, MA2 pin
acts as an EEDO pin that reads in the output data stream from
the EEPROM. After the EEPROM auto load sequence is done,
this pin becomes MA2. Together with MA[19:3], they form the
packet buffer address lines 19 - 0.
45
MA18(RXD1)
I/O, 4ma
44
MA17(RXD2)
I/O, 4ma
43
MA16(RXD3)
I/O, 4ma
24
MA2(EEDO)
I/O,4ma
135
134
142
88
RDB
WRB
INTB
DREQB
I, TTL
I, TTL
O/D, 4ma
O, 4ma
Host Bus Read Indicator : Active low. (Internal pull-up)
Host Bus Write Indicator : Active low. (Internal pull-up)
Host Bus Interrupt Output : Active low.
DMA Burst Read Request : Active low to request a burst
read transfer.
DMA Read Acknowledge : Active low during the burst
read cycle.
Host Bus Reset Input : Active low. (Schmidt trigger input,
Internal pull-up) Input delay is typically 7ns, minimum
RSTB pulse width must be 5 Tclk,Tclk=1/50MHz.
Host Bus Chip Select Input : Active low to enable access
to GMAC, set to disable access to GMAC. But the net-
work activity is independent of this signal. (Internal pull-
down)
Host Bus Width 16 bit / 32 bit select : Set for the 16 bit
host bus, reset for the 32 bit host bus.
89
DACKB
I, TTL
130
RSTB
I,TTL
90
CSB
I,TTL
91
H16_32
I,TTL
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相關代理商/技術(shù)參數(shù) |
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| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
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| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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