參數(shù)資料
型號: MX98727
英文描述: SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
中文描述: 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器
文件頁數(shù): 38/71頁
文件大?。?/td> 389K
代理商: MX98727
38
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Removing packets from the buffer ring
Packets are removed from the buffer ring inside the
packet memory by the host through two ways, namely,
host DMA and IO mode. The host DMA uses DACKB
and DREQB signals to conduct read or multiple reads (
burst reads ) on the chip. The other way is so called IO
mode read or burst reads to register 43h-40h of the chip.
This 32 bit port is also called RRD data port. When
DREQB = 0, the host can still do both read and write
accesses to GMAC's internal registers.
DREQB is asserted by the chip whenever there is at
least one receive packet inside the buffer ring and at
least one burst transfer is ready inside the chip's on
chip fast buffer. Host can issue DACKB or IO read at
RRD port to read out the data whenever the DREQB =
0. The chip will keep track of the DMA byte count auto-
matically and issue an interrupt at the end of host DMA
depending on the set up of receive interrupt conditions.
The actual packet memory address contains two parts,
the higher address lines consists of RRP register bit
[11:0] and the lower address lines are provided by the
RRPBC counter. By reading the descriptor, the device
driver will know the size of the packet and it can move
data up to the last page without updating the RRP regis-
ter. The RRP register will be automatically updated by
GMAC (if AUTOPUB bit=0) whenever a page is ex-
hausted. GMAC also will properly link the RRP to the
next page pointed to by the BP register if the RHBP
page is exhausted. The device driver does have the
right to "overwrite" the content of the RRP register at
any time.
The configuration register GCA (32h) bit 5 is
"AUTOPUB", when 0 meaning all page registers for the
host side will be updated by GMAC automatically. The
content of GCA can be loaded by GMAC from EEPROM
automatically right after the system hardware reset. If
AUTOPUB is 1, it means no automatic update of these
host page registers ( RRP, TWP ). Default is 0 for the
automatic host page registers update. So both the auto-
matic and the manual RRP pointer updates are avail-
able for the device driver. The following is a suggested
method for maintaining the receive buffer ring pointers :
1. At initialization, set up BP= RRP=RWP and RHBP to
a higher memory page. At this point, the receive buffer
is empty.
2. Setup a software address counter and a byte counter
to keep track of the packet being removed from the
packet memory to the host. After a packet is removed,
the RRP is increment by GMAC so that RWP will not
overwrite a page which is part of an unprocessed
packet.
3. After a packet is stored in the receive buffer ring,
GMAC may assert an interrupt.The device driver will
start moving data beginning from the page pointed to
by the RRP register. It reads the packet length and
advanced the address counter the same as the DMA.
Care should be taken when the RHBP page is ex-
hausted or the buffer is full if the manual page pointer
update is used .
Possible junk data of burst transfer
Burst read length can be programmed through register
50.1 and 50.0 bit. Length can be 1 , 2 or 4. It is possible
to have extra junk bytes in the last burst transfer.
When H16_32=1 (16 bit host), regardless of burst length,
all burst transfer will end at 8 bytes boundary. Therefore,
possible junk bytes could be 1 byte to 7 bytes.
When H16_32=0 (32 bit host), regardless of burst length,
all burst transfer will end at 16 bytes boundary. There-
fore, possible junk bytes could be 1 byte to 15 bytes.
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