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參數(shù)資料
| 型號(hào)： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 46/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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46
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
5.3 Receive interrupt
Normally the interrupt will be asserted after a packet is
received. Either RI or REI will be set to indicate such an
event. Sometimes, it is desirable not to report every
single reception using the interrupt. GMAC has incorpo-
rated a receive packet counter and an interrupt timer (
RXINTT) to control the receive interrupt condition. By
these two logic, we can issue the receive interrupt based
on the receive packet count or the RXINTT time out,
whichever comes first. So the receive interrupt logic can
be expressed as follows:
Assert RI ( or REI ) interrupt if ( RXINTC is reached ) or
( RXINTT has timed out )
Receive Interrupt Timer : Register 15h and 14h forms a
16 bit timer running at 25Mhz. Default is 0000h, mean-
ing no time-out is used on the RI or REI interrupt asser-
tion. Reg15h.7 is the RXINTT.15 bit and Reg14h.0 is the
RXINTT.0 bit. Any non-zero value enables the time out
function. The possible time-out period ranges from 40ns
to 2621 us. The RXINTT timer will be started after the
last packet ( within the RXINTC range ) is transfered to
the packet memory (RINTSEL=0) or the host memory
(RINTSEL=1) and the timer will be reset when the inter-
rupt is generated. When the received packet count has
not reached the RXINTC [1:0] before the RXINTT time-
out, an interrupt will be generated by the RXINTT time-
out alone.
Receive Interrupt Counter : Register 01h bit 7 and bit 6
define the number of packets received before the re-
ceive interrupt RI or REI can be asserted. This function
is independent of the RXINTT timer's ( Reg.15h/14h )
time-out. Whenever either a time-out or a packet count
is reached, a receive interrupt will be generated. Default
is 00h after reset, meaning the normal receive interrupt
operation which asserts RI or REI after a single packet
received and no RXINTT timer is used. Non-zero value
in these two bits will enable this special receive interrupt
operation.
RXINTC1
RXINTC0
Interrupt received
packet count
0 0 1 ( default )
0 1 2
1 0 4
1 1 8
5.4 Bus integrity check
Sometimes, it is necessary to have a hardware check-
ing mechanism which constantly monitoring the host
activity for any abnormal situation.The host bus hang
problem is sometimes seen in many systems. GMAC
provides a monitoring logic that watches out for any ab-
normally long cycle on the host interface. A timer called
the BICT ( register 1Dh ) timer is used, which is an 8 bit
counter running at 25MHz or 40ns per clock. Default is
00h, meaning no bus integrity check is enabled. Value in
this counter other than zero will enable the bus integrity
check. Any bus cycle that longer than the time-out pe-
riod defined in this timer will cause termination of the
current bus cycle so that this abnormal bus hang and
bus dead lock can be recovered. The BUSEI Interrupt (
register 09h bit 6 ) will be issued in this case. The pos-
sible time-out period ranges from 40ns to a maximum of
10.24us. As soon as a cycle is being processed by
GMAC, this timer is started and the counter is reset
when the cycle is normally finished before the time out.
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