參數(shù)資料
型號: MX98727
英文描述: SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
中文描述: 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器
文件頁數(shù): 47/71頁
文件大?。?/td> 389K
代理商: MX98727
47
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
5.5 Host Receive DMA Fragment Counter
In order to allow host to predict an insufficient host buffer
problem before the actual host DMA takes place. The
chip provide a fragment counter which can be used to
"down count" the host DMA byte length and automati-
cally compare the content to the length of the next re-
ceive packet. If the length fo the next receive packet is
larger than the content of this counter then DREQB will
be disabled temporarily until the count is programmed a
new value which is larger than the length of next receive
packet.
Flow Chart of Fragment Counter Programming
Typical application is that host set the initial counter
value to indicate the amount of free host buffer for re-
ceive packets. When host buffer has been filled with
packets and remaining free buffer might be smaller
than the length of next receive packet then the chip can
interrupt the host, if register 8.0 FRAGIM bit is set.
Register 9.0 FRAGI will be set after host DMA of cur-
rent packet is finished to indicate this interrupt and DMA
is temporarily disabled so that host can allocate more
free buffer to prevent "fragment" in the host buffer. Reg-
ister 54h, 55h and 56h are defined as fragment counter
which are all 0 after reset. When the counter is 0, this
fragment counter logic is disabled, no down counting or
interrupt will be valid.
After Initialization
Write a non-zero value to the
counter as byte count
DREQB is asserted
DREQB is deasserted
FRAGI is asserted
Host DMA resume
Reload FRAGCNT
Clear FRAGI
MAC has more RX
packets for host
Compare
incoming packet
length > FRAGCNT
YES
YES
NO
NO
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