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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 45/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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45
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Transmit FIFO threshold of the transmit DMA
The transmit FIFO threshold is defined by Register 33h
bits [1:0] (TTHD [1:0]). TTHD is used to control the ag-
gressiveness of the transmit DMA request for the packet
longer than 1518 bytes in the packet memory bus arbi-
tration. For example, the default value of TTHD=1/2
depth of the transmit FIFO means whenever the content
of FIFO falls below 1/2 of the FIFO space, the transmit
DMA will have higher prority over the receive DMA if the
receive FIFO is not critical. If the transmit FIFO is over
the TTHD level, then transmit may have equal priority
as receive DMA or lower priority to the receive DMA if
the receive FIFO is critical. The larger the TTHD thresh-
old, the more aggressive the transmit DMA and it takes
more time for the transmit DMA to become critical of
running empty. The small TTHD will result in less ag-
gressive transmit DMA but then it is also more critical of
running the FIFO empty (underrun error). Since the
packet memory bandwidth is shared by the host, the
transmit DMA and receive DMA, "tuning" TTHD may be
necessary for the best network/system throughput.
Transmit DMA
Transmit DMA normally has higher priority over the host
but lower than the receive DMA. The physical address
of receive DMA is formed by cascading a page address
RWP register and the RWPBC counter for the receive
DMA. RWP [11:0] is mapped to MA[19:8] while the
RWPBC counter is mapped to MA[7:0]. Thus a 20 bit
MA address is derived. RWP will be automatically up-
dated by GMAC whenever a page is exhausted. If RHBP
is reached, GMAC will link BP as the next available page
into RWP if the BP page is free.
5.2 Local DMA
Receive FIFO threshold of the Receive DMA
The receive FIFO threshold is defined by register 33h
bit [3:2] (RTHD[1:0]). It is used to control the aggres-
siveness of the receive DMA request in the packet
memory bus arbitration. For example, the default value
of RTHD=1/2 depth of the receive FIFO means when-
ever the contents of the FIFO are over 1/2 of the FIFO
space, it becomes "critical" since the FIFO may soon
be full or overrun. When the receive FIFO is "critical",
the receive DMA will have higher priority over the trans-
mit DMA (regardless of whether the transmit FIFO is
critical or not). If the FIFO is not over the RTHD level, it
is not critical. The transmit DMA may have equal prior-
ity as the receive DMA or higher priority over the receive
DMA if the transmit FIFO is critical. The larger the re-
ceive threshold, the less aggressive the receive DMA
because it takes more time for the receive DMA to be-
come critical. It also presents a higher risk to become
FIFO full or to overrun the FIFO space. The smaller the
RTHD, the more aggressive the receive DMA is and less
risk in running into a FIFO full condition, but it also blocks
other accesses from the host and the transmit DMA.
Since the packet memory bandwidth is shared by the
host, the transmit DMA and the receive DMA, "tuning"
the RTHD threshold may be necessary for the best net-
work/system throughput.
Receive DMA
The receive DMA normally has higher priority over the
host and the transmit DMA. This is due to the receive
data can not be reproduced locally. Therefore it is more
urgent than others. The physical address of the receive
DMA is formed by cascading a page address RWP reg-
ister and the RWPBC counter for the receive DMA. RWP
[11:0] is mapped to MA[19:8] while the RWPBC counter
is mapped to MA[7:0]. Thus a 20 bit MA address is
derived. RWP will be automatically updated by GMAC
whenever a page is exhausted. If RHBP is reached,
GMAC will set RWP as BP if the BP page is available.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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