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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 12/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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12
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Last Transmitted Packet Status: LTPS ( Reg4h), RO, default=00h
Bit
4.0
4.1
4.2
4.3
Symbol
CC0*
CC1*
CC2*
CC3*
Description
Collision Count Bit 0 :
Collision Count Bit 1 :
Collision Count Bit 2 :
Collision Count Bit 3 : When CC[3:0] = 1111 and a new collision is detected, it is
called the excessive collision error which will abort the current packet. The TEI inter-
rupt bit will be set.
Carrier Sense Lost : Set to indicate CRS was lost during the transmission. Default is
reset for the normal packet transmission.
TX FIFO Underflow : Set to indicate a underflow problem in the TX FIFO. An FIFOEI
interrupt is generated for the driver to resolve this problem.
Out of Window Collision : Set to indicate a collision occurred after 64 bytes of data
has been transmitted. No retransmission will be issued.
Transmit Error: Set to indicate the packet transmitted with error. Reset for the normal
packet transmission.
4.4
CRSLOST*
4.5
UF*
4.6
OWC*
4.7
TERR*
Last Received Packet Status: LRPS ( Reg5h), RO
Bit
5.0
5.1
Symbol
BF*
CRC*
Description
RX Packet Buffer Full Error : 1 indicates the RX packet buffer is full.
CRC error : The calculation is based on the integer multiple of bytes. Set to indicate the
CRC error for the received packet.
Frame Alignment Error : Set to indicate an extra nibble is received which is not at the
octet boundary. This error is independent of the CRC detection.
FIFO Overrun : When set, an interrupt is generated. The driver must resolve this error.
Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes. An interrupt
will be generated to the driver.
Multicast Frame address : Set to indicate the current frame has the multicast address.
Runt Frame : Set to indicate a frame length less than 64 or 60 bytes depending on
register 50.2 ( RUNTSIZE ), only meaningful when the Reg01h.3 PB bit is set. When
PB=1, a runt frame will be accepted & RI is set for receive interrupt. When PB=0, a runt
frame is rejected.
Receive Error : Set to indicate a packet received with errors including CRC, FAE, FO,
RW error.
5.2
FAE*
5.3
5.4
FO*
RW*
5.5
5.6
MF*
RF*
5.7
RERR*
Notes : This LRPS register contains the same status byte as in the description field of the last received packet in
the packet memory.
3.6
BFS1*(MDO)
Normally used as BFS1 pin for test purpose, while in MII mode, it is
used as MII management write data (MDO) for MDIO pin's output data.
Normally used as BFSTATUS pin for test purpose, while in MII mode, it is
used as MII management read data (MDI) for MDIO pin's input data.
3.7
BFSTATUS*(MDI)
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相關(guān)代理商/技術(shù)參數(shù) |
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