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參數(shù)資料
| 型號(hào)： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 21/71頁(yè) |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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21
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Reserved Register : RESERVED (Reg39h/38h), R/W, default=0000h
Bit
38.7-0
39.7-0
Symbol
RESERVED
RESERVED
Description
Default = 00h
Default = 00h
Host Interface Protocol Register: Reg3Ah, R/W, default=00h
Bit
3A.0
Symbol
WRDYB
Description
Write Packet Memory Ready Bar Status Indication : It is used to indicate whether
the TWD port is ready for the next write. Read only. 1 indicates the host can not
issue a new write cycle into the TWD data port. 0 indicates the host can issue a
new write cycle into the TWD port. This bit is primarily used by the host who does
not use the SRDY pin.
Start IORD read/Read Ready Bar : Write 1 to start the IORD port read. When data
is ready for the host in the IORD port, this bit becomes 0 indicating a "read ready".
So the host needs to poll this bit for 0 before he can issue a read to the IORD port.
Reading a 1 indicates data is not ready in the IORD port yet. This bit is primarily
used by the host who does not use the SRDY pin.
DREQB pin status bit : A direct reflection of the DREQB pin which can be read to
inquire whether there are any RX packet data available in the RRD port. This bit is
primarily used by the host who does not use the DREQB pin.
3A.1
STIORD/RRDYB
3A.2
DREQB
IO Mapped Data port: TWD (Reg34h/35h/36h/37h), WO
Bit
34.7-0
35.7-0
36.7-0
37.7-0
Symbol
TWD[31:0]
Description
Transmit Write Data Port : The 32 bit data port is used for writing the packet data into
the transmit buffer ring. In the 32 bit mode, i.e. H16_32=0, reg37h is the MSB byte
(byte3), and reg34h is the LSB byte (byte 0). In the 16 bit mode, i.e. H16_32=1, reg35h
is the MSB byte (byte 1) and reg34h is the LSB byte (Byte 0). Access to this port will
be mapped to the packet buffer pointed to by the TWP page pointer and the internal
byte counter TWPBC. No burst is supported for either read or write. Any access to
this port will increment the TWPBC by either 2 or 4 depending on H16_32. This is
usually used by the driver to prepare TX packets. If host system does not support
SRDY pin, then register 3A bit 0 ( WRDYB ) can be used to handshake with GMAC
during the data port write cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
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