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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 20/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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20
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
GMAC Configuration A Register: GCA (Reg 32h), R/W, default=00h
Bit
32.0 BPSCRM
Symbol
Description
Bypass Scrambler: Default is 0, meaning enable the 100 TX scrambler. Set to disable the
scrambler for the 100 TX mode.
Packet Buffer Data Width : Default is 0, meaning the packet buffer data width is byte. Set
when the packet buffer data width is 16 bits.
Normally reset, SRAM Taa must be less than 25ns, set to use -70ns SRAM or better
Accept RX packet with error : Default is reset to receive packets with error, set to reject
packets with error, packet memory will not contain packet with RW, FO, CRC errors.
Default = 0 after reset, on-chip tranceiver is used. Set by software to enable MII interface.
Auto Page Update option :
Set to disable the automatic host page update during the host DMAs. Reset to enable the
host page update for the RRP, TWP registers. Default is reset.
Default=0, after rest which means Reg 3E & 3F (TXFIFOCNT) are not used. This option is
only good for a byte-base host transfer. For host which do word/double word transfer, this
bit must be set to 1 to force TXFIFO use actual packet length for transmission.
Default = 0.
32.1 PBW
32.2 SLOWSRAM
32.3 ARXERRB
32.4 MIISEL
32.5 AUTOPUB
32.6 TXFIFOCNTEN
32.7 RESERVED
GMAC Configuration B Register: GCB (Reg33h), R/W, default=00h
Bit
33.1-0
Symbol
TTHD[1:0]
Description
Transmit FIFO Threshold : Default is 00
TTHD1
TTHD0
0
0
0
1
1
0
1
1
Receive FIFO Threshold : Default is 00
RTHD1
RTHD0
0
0
0
1
1
0
1
1
SRAM Early Latch Enable : Default = 0. Set to enable.
X4 FIFO Early Latch Enable : Defautl = 0. Set to enable.
DREQB NEW Timing Enable : Default = 0. Set to enable.
FIFO depth
1/2
1/4
3/4
reserved
aggressiveness
medium
least
more
reserved
33.3-2
RTHD[1:0]
FIFO depth
1/2
1/4
3/4
reserved
aggressiveness
medium
most
least
33.4
33.5
33.6
33.7
SRAMELEN
X4ELEN
DREQB2EN
reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
| MX98902A(PLCC) | LAN Node Controller |
| MX98902A(PQFP) | LAN Node Controller |
| MX98902A(SQFP) | LAN Node Controller |
| MX99011MC | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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