24
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
RX Burst Read Data Port : RRD[31:0] (Reg40h~43h), RO, default=XXXXXXXXh
Bit
40.7-0,
41.7-0
42.7-0
43.7-0
Symbol
RRD[31:0]
Description
RX Read Data Port : The 32 bit read only data port for the RX buffer ring.
The MSB byte (byte 3) is Reg43h and The LSB byte (byte 0) is Reg40h
if H16_32=0. Reg41h is the MSB byte (byte 1 ) and Reg40h is the
LSB 43.7-0 byte (Byte 0) if H16_32=1.The RX buffer ring accessed by this
port is pointed to by RRP and RRPBC. When 4 consecutive double words
(4x4 bytes if H16_32=0, or 4x2 bytes if H16_32=1) are ready inside GMAC,
DREQB will be asserted and burst transfers can be issued through the use
of DACKB. GMAC will maintain the burst read buffer's integrity in both cases.
This port is used to fetch RX packets.
Bit
3E.7-0
Symbol
TXFIFOCNT[7:0]
Description
TX FIFO Send Byte Count bits [7:0]: Together with TXFIFOCNT[11:8] forms a 12
bits TX FIFO byte count for the direct FIFO mode.
TXFIFOCNT[11:8] TX FIFO Send Byte Count bits [11:8]: Together with TXFIFOCNT[7:0] forms a 12
bits TX FIFO byte count for the direct FIFO mode. Software must program
TXFIFOCNT[11:0] with exact packet length in bytes before command GMAC to
start transmit ( ST0, ST1 ). Since host bus is either word or double word mode. A
exact byte count must be programmed for TX channel to send out data and CRC
correctly.
3F.3-0
ID2 (Reg46h/47h), RO, default="0001"
Bit
46.7-0,
47.7-0
Symbol
Description
ID2[15:0]
ID2 16 bit code : Reg47h is the MSB byte, which is set to 00h. Reg46h is
the LSB byte, which is set to 01h.
ID1 (Reg45h/44h), RO, default="MX"
Bit
44.7-0,
45.7-0
Symbol
Description
ID1[15:0]
ID1 16 bit code : Reg45h is the MSB byte, which is set to "M". Reg44h is the
LSB byte, which is set to "X".
TX FIFO Byte Counter (Direct FIFO Mode) : TXFIFOCNT, Reg3F/3Eh, R/W