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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 37/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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37
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
If device driver choose AUTORCVR = 0, the following
procedure is suggested for the device driver to recover
from such an error situation manually.
1. Issue the SR=0 ( NCRA register bit 3 ) which will stop
RX channel to prevent new data from coming into RX
FIFO.
2. Issue RX FIFORST to clean RX FIFO.
3. Remove all the received packets in the packet memory.
When buffer ring is empty, RRP=RWP.
4. Clear all receive related interrupt flags and then set
the SR bit=1 to resume the receive operation.
Successful reception
Based on the network address filtering modes set up by
the device driver, GMAC will determine whether to re-
ceive a packet or to reject it. It either branches to a
routine to store the packet or to another routine to re-
claim the buffers used to store the packet. If a packet is
successfully received, GMAC will store the receive sta-
tus , the packet length and the next packet pointer in the
receive descriptor located at the beginning of the first
page of the packet and the status in the LRPS ( register
05h ) register. Note that the remaining bytes in the last
page are discarded and reception of the next packet
begins on the next empty 256-byte page boundary. The
RWP is then set by GMAC to the next available page in
the buffer ring.
Receive Write
Page Pointer
Packet
Ends
Receive Read
Page Pointer
Packet Status
Figure 4.2.4 Termination Of Received Packet-Packet Accepted
Next Package Page Pointer
Packet Length
Receive Status
4
3
2
1
n
n-1
n-2
Rejected packets
If the packet is a runt packet and the PB bit ( Pass Bad
option, register 01h, bit 3 ) is 0, then it is rejected. The
buffer previously used by this rejected packet is re-
claimed by resetting the internal byte counter to zero
automatically by GMAC. Packets with at least 64 or 60
bytes defined by register 50.2 ( RUNTSIZE ) are always
received and stored regardless of the CRC error status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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