參數(shù)資料
型號(hào)： MX98727
英文描述： SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
中文描述： 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 35/71頁(yè)
文件大?。?/td> 389K
代理商： MX98727
35
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
4.2 Packet Reception
The local DMA receive channel uses a receive buffer
ring structure comprised of a series of contiguous fixed
length 256-byte ( 128 word ) buffers for storage of re-
ceived packets. The location of this receive buffer ring
is programmed in two page pointers, the Boundary Page
pointer and the Receive High Boundary Page pointer.
Ethernet packets consist of a distribution of shorter link
control packets and longer data packets, the 256-bytes
buffer length provides a good compromise between dif-
ferent packet sizes to best utilize the memory. The re-
ceive buffer ring provides storage for back-to-back pack-
ets in a loaded network. The assignment of buffers for
storing packets is managed by the GMAC's receive DMA
logic. Three basic functions are provided by the receive
DMA logic : linking receive buffers for long packets, re-
covery of buffers when a packet is rejected and recircu-
lation of buffer pages that has been read by the host.
BUFFER 1
BUFFER 2
BUFFER 3
PAGE
RHBP
BP
Packet Memory
256 BYTES
Figure 4.2.1 GMAC Receive Buffer Ring
4
3
2
1
n
n-1
n-2
Receive Write
Page Pointer
Boundary
Page Pointer
Receive High
Boundary
Page Pointer
256 BYTES
Figure 4.2.2 GMAC Receive Buffer Ring at Initialization
4
3
2
1
n
n-1
n-2
Receive Read
Page Pointer
Initialization of the receive buffer ring
Two static page pointer and two working page pointers
control the operation of the receive buffer ring . These
are the Boundary Page ( BP ) pointer, the Receive High
Boundary Page ( RHBP ) pointer, the Receive Read Page
( RRP ) pointer and the Receive Write Page ( RWP )
pointer. The BP register points to the first buffer ( page
) of the receive buffer ring. RHBP points to the last page
of the receive buffer ring. The RWP register points to
the page in which the receive DMA logic is storing the
incoming network data. The RRP register points to the
page from which the host will read the next network data.
A receive descriptor structure is located at the begin-
ning of the start page of a received packet. If GMAC
ever reaches the page pointed to by the RHBP register,
it will link the page pointed to by the BP register as the
next page, thus forms a ring buffer structure.
The size of the receive buffer ring is the total buffer space
between the BP and the RHBP registers. An internal 8
bit byte counter ( RWPBC ) accounts for MA[7:0] will be
used with the RWP register to form a physical memory
address during the receive DMA write operation. This
RWPBC counter will track the actual location within a
page. After GMAC is initialized, BP, RWP and RRP
should all point to the same page. These registers must
be properly initialized before setting the register 00h SR
( bit 3 ) bit to 1 which enables the receive channel for the
DMA function.
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