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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 36/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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36
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Begin Storing
Packet
Receive Write
Page Pointer
4 Byte Offset For
Packet Descriptor
Begin Data
Reception
Figure 4.2.3 Received Packet Enters the Receive Buffer Pages
4
3
2
1
n
n-1
n-2
Receive buffer ring full
In a heavily loaded network which may cause overflow
of the receive buffer ring, when the last available page
is exhausted and more data needs to be stored for the
current packet then the receive buffer ring is full but
GMAC will continue receiving until RX FIFO is also over-
flow. At this point, GMAC will do the following actions :
1. Close current received packet with the FO bit ( bit 3 )
and the BF bit ( bit 0 ) of the receive descriptor being
set if a minimum of one page is used by this packet.
2. An interrupt may be asserted if the RBFI ( register
09h bit 7 ) interrupt bit is set and the RBFIM bit (
register 08h bit 7 ) is also set.
3. If AUTORCVR is set, then the last packet with FO,
BF error will be discarded from the packet memory
and from RX FIFO as well and receiving is resumed
for next packet.
4. If AUTORCVR is reset, then GMAC can not receive
any more packet. All following packets will be lost
and MPC ( Missed Packet Counter ), registers 07h
and 06h, will be increment automatically. MPC can
be reset by the device driver.
Beginning of reception
After all four page pointers are properly set by the de-
vice driver ( the host ), the register 00h SR bit can be set
to enable the reception of packets. When the first packet
arrives, the GMAC begins storing the packet at the lo-
cation pointed to by the RWP register. 4 bytes ( descrip-
tor ) are saved in this first page to store receive status
corresponding to this packet. Whenever the internal byte
counter reaches FFh indicating the end of a page, RWP
will be increment by 1 automatically if more data of the
packet is arriving.
The incoming network address is examined by GMAC
to determine whether to accept or reject. If GMAC de-
cides to reject the packet, then the receive FIFO will
restore all spaces used by the rejected packet ( called
restore ). If the packet should be accepted and the RX
FIFO contains data up to a threshold level which can be
programmed by RTHD[1:0] ( register 33h bits [3:2] ). The
smaller the threshold, the faster the receive DMA logic
removing data from FIFO, thus may has lower risk in
running into a FIFO overrun situation. The disadvantage
of a smaller threshold is that the host and the transmit
channel may have less bandwidth of the packet memory.
So RTHD threshold should be chosen to tune for the
best network throughput. The default value of the receive
FIFO threshold is 00, meaning 50% of the FIFO is filled
up before any receive local DMA can start removing
data out of the FIFO.
Linking receive buffer pages
If the packet exhausts the first 256-bytes buffer, the re-
ceive DMA logic will perform a forward link to the next
buffer to store the remainder of the packet. For a maxi-
mum length packet , up to 6 buffers can be linked to-
gether. Buffers can not be skipped when linking. There-
fore a packet will always be stored in contiguous buff-
ers. Before the next page can be linked, the receive DMA
logic does two comparisons.
The first comparison tests the equality between the con-
tent of the RWP register + 1 and the content of RRP
register. If equal, the reception is aborted. This is called
the receive buffer full error. Second comparison tests
the equality between the RWP register and the RHBP
register. If equal, the receive DMA will restore RWP to
the first buffer in the receive buffer ring pointed to by the
BP register if the receive buffer ring is not full.
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