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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 26/71頁 |
| 文件大小： | 389K |
| 代理商： | MX98727 |
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26
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
MISC Control Register 2 : MISC2, Reg50h, R/W, default=00h.
Bit
50.0
Symbol
HBRLEN0
Description
Host Burst Read Length control bit 0 : Together with HBRLEN1 define the
length of the burst read access.
Host Burst Read Length control bit 1 : Together with HBRLEN0 define the
length of the burst read access.
HBRLEN1
HBRLEN0
burst length
0
0
x4
0
1
x1
1
0
x2
1
1
x4
Runt Frame Size Select bit : Default is 0, meaning the runt frame is defined
as less than 64 bytes. Set to define the runt frame as less than 60 bytes.
DREQB timing Control : Default is 0, meaning DREQB is deasserted after
the data transfer. If set, DREQB deassertion is earlier than the end of the
data transfer. See the timing diagram for details.
Receive Interrupt timing Select : Default is 0, which asserts RI and REI at
the end of the receive local DMA. If set, assert RI and REI at the end of the
host receive DMA. It also defines the RXINTT's & RXINTC's counting tim-
ing. See the timing diagram for details.
reserved for internal test probing select.
Default=0, A11 to A8 are internally grounded. set this bit to enable A11 to A8
decoding. This bit is ignored if MIISEL = 1 in MII mode.
Auto RX Full Recovery: Default is reset meaning when RX buffer full and
RX FIFO overflow happen at the same time, GMAC will stop receiving until
host clear up RX FIFO and RX full condition. Set to enable GMAC to re-
cover from such error automatically , the last packet with such error will be
discarded in the packet memory and RX FIFO will be cleared at the end of
current receiving, and then receiving is resumed for next packet.
50.1
HBRLEN1
50.2
RUNTSIZE
50.3
DREQBCTRL
50.4
RINTSEL
50.5
50.6
ITPSEL
A11A8EN
50.7
AUTORCVR
Host Receive Packet Counter : HRPKTCNT, Reg53/52h, RO
Bit
52.7-0
Symbol
HRPKTCNT[7:0]
Description
Host Receive Packet Count [7:0] : Together with HRPKTCNT[15:8] forms a
16 bits counter. Cleared after a read access to this register.
Host Receive Packet Count [15:8] : Together with HRPKTCNT[7:0] forms a
16 bits counter. Counter is increment only at the beginning of a received
packet's last host DMA cycle. A read access to this register will clear the
counter to 0 right at the end of this read cycle. This counter records the
total receive packet count since previous read access to this counter.
53.7-0
HRPKTCNT[15:8]
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PDF描述 |
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| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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