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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 33/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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33
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Transmit packet assembly format in the packet
memory
For the 16 bit SRAM interface :
D15
D8
D7
D0
Descriptor Byte 1
Descriptor Byte 0
Descriptor Byte 3
Descriptor Byte 2
Destination Address Byte 1
Destination Address Byte 0
Destination Address Byte 3
Destination Address Byte 2
Destination Address Byte 5
Destination Address Byte 4
Source Address Byte 1
Source Address Byte 0
Source Address Byte 3
Source Address Byte 2
Source Address Byte 5
Source Address Byte 4
Type/Length byte 1
Type/Length byte 0
Data byte 1
Data byte 0
For the 8 bit SRAM interface :
D7
Descriptor Byte 0
Descriptor Byte 1
Descriptor Byte 2
Descriptor Byte 3
Destination Address Byte 0
Destination Address Byte 1
Destination Address Byte 2
Destination Address Byte 3
Destination Address Byte 4
Destination Address Byte 5
Source Address Byte 0
Source Address Byte 1
Source Address Byte 2
Source Address Byte 3
Source Address Byte 4
Source Address Byte 5
Type/Length byte 0
Type/Length byte 1
Data byte 0
D0
Multiple packets transmission ( TX local DMA
mode only )
If more packets are prepared in the packet memory and
all transmit descriptors are set properly ( i.e. next packet
page pointer, packet length, OWN bit = 1, etc), then a
TX DMA poll command can be used to send out all these
packets at once. As soon as the first packet transmis-
sion is done, an interrupt will be asserted to get the host
attention. The device driver can serve this interrupt by
processing all the packets that have the OWN bit set to
zero in this multiple packets list in the packet memory.
The device driver can "peek" the OWN bit of the next
packet's descriptor to see if there are more packet(s)
transmitted completely at that point. If the OWN bit of
the next packet's descriptor is zero, then the device driver
can proceed to the next packet after finishing the cur-
rent packet. When all packets are transmitted success-
fully or aborted, register 00h. ST1 and ST0 bits are inter-
nally reset. This way, packets can be sent out in a burst
with a single transmit command.
The IORD port and the IORDP page pointer together
can be used to access all the previous packet transmis-
sion status. Since the IORD port will read data from the
packet memory, the SRDY pin must be used for pos-
sible wait states caused by the packet memory's arbi-
tration. If the system application does not support the
SRDY pin, then register 3A.1 ( STIORD/RRDYB ) can
be used to read data from the IORD port in a handshake
manner.
相關(guān)PDF資料 |
PDF描述 |
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| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
| MX98902A(PLCC) | LAN Node Controller |
| MX98902A(PQFP) | LAN Node Controller |
| MX98902A(SQFP) | LAN Node Controller |
| MX99011MC | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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