參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 99/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 70 of 122
2.34 DMAn_Transaction Count Registers (n=0~1)
DMA0_Transaction Count Register (DMA0_TRN_COUNT)
<Address : H’4E>
DMA1_Transaction Count Register (DMA1_TRN_COUNT)
<Address : H’56>
b15
14
13
12
11
10
9876
54321
b0
TRNCNT
0000
000000
0
00000
----
------
----
------
<H/W reset : H'0000>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15~0
TRNCNT
Transaction Count
<TREN bit = "0">
Packet count that completes the receiving
(behaving as the compare register)
<TREN bit = "1">
Read
The number of the received packets (behaving as the current
register)
Write
Packet count that completes the receiving
(behaving as the compare register)
(1) TRNCNT (Transaction Count) Bits (b15~b0)
This register is used under the following conditions:
When set to OUT buffer (EPi_DIR bit = ”0”).
When set to continuous receive mode (EPi_RWMD bit = ”1”).
When set to bulk transfer mode (EPi_TYP bits = ” 01”)
When accessing using Dn_FIFO Data Register.
With the transaction count function set to be enabled (TREN bit = “1”), the following conditions are added to
the buffer receive completion condition. In case of the receive completion, refer to the “EPi_RWMD bit of the
EPi Configuration Register 0”.
When the value set by this register conforms to the packet receive count.
(Conformity between current register and compare register; See below.)
This register is composed of two registers as follows:
Current register
:Counting of the received packet number (counts up at the TREN bit = “1”)
Compare register :The value that completes the receiving
It is necessary to clear the TNCNT bits as the current register to “0” by writing “1” to the TRCLR bit before the
next transfer.
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相關代理商/技術參數(shù)
參數(shù)描述
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