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參數(shù)資料
| 型號： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 119/128頁 |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 88 of 122
3.3.4
DMA Transfer Overview
The M66291 is capable of DMA transfer in 16-bit/8-bit width (specified by the Octl bit) against the endpoint 1
to 6.
The DREQ pin is asserted when the endpoint buffer set to the Dn_FIFO Select Register is in read/write ready
state. The output of DREQ pin is enabled by the DMAEN bit.
In order to write the data to transmit the short packet by the DMA_FIFO, assert the TC pin or set the IVAL
bit to “1” after writing last data.
Further, when read by using DMA, the timing of the buffer ready interrupt occurrence can be changed by the
INTM bit.
3.3.5
DMA Transfer Method
The DMA transfer method is set by the DFORM bit of the Dn_FIFO Control Register.
(1) Cycle Steal Mode (BUST bit = "0")
At cycle steal mode, the DREQ pin is asserted at every transfer (8-bit/16-bit).
(A-1) DMA transfer control by the DACK pin and read/write pins (DFORM bits = “00”):
At this mode, the DACK pin and read/write pins are used to access to the Dn_FIFO Data Register
of the M66291.
(A-2) DMA transfer control solely by the DACK pin (DFORM bits = “01”):
At this mode, only the DACK pin is used to access to the Dn_FIFO Data Register of the M66291.
The read/write pins are not used in this mode (are ignored).
(A-3) DMA transfer control by the chip select pin and the address pins (DFORM bits = “10”):
In this mode, the address pins and read/write pins are used to access the Dn_FIFO Data Register
of the M66291. The DACK pin is not used in this mode (is ignored).
(2) Burst Mode (BUST bit = "1")
At burst mode, the DREQ pin is asserted until all data in the buffer has been transferred , and is negated
when the transfer completes.
(B-1) DMA transfer control by the DACK pin and read/write pins (DEFORM bits = “00”):
This mode operates with the same timing as (A-1).
(B-2) DMA transfer control by the chip select pin and address pins (DEFORM bits = “10”):
This mode operates with the same timing as (A-3).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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