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參數(shù)資料
| 型號： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 106/128頁 |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 77 of 122
(4) EPi_Buf_siz (Buffer Size) Bits (b11~b8)
These bits set the buffer size in 64-byte unit (Note).
When set to double buffer mode (EPi_DBLB bit = “1”), the buffer double in size set by these bits is used.
Set the values to these bits as follows:
Continuous transmit/receive mode
: Value set by this register > Value set by the EPi_MXPS bits
Single transmit/receive mode
: Value set by this register ≥ Value set by the EPi_MXPS bits
Set in the manner as follows (single transmit/receive mode only) to write “1” to the IDLY bit at isochronous
transfer mode (set by EPi_TYP bits):
Single transmit/receive mode
: Value set by this register > Value set by the EPi_MXPS bits
When set to IN buffer (EPi_DIR bit = “1”), if the integral multiples of the value set by the EPi_MXPS bits is set
to these bits, the zero-length packet can be added after all data are transmitted. For details, refer to the
setting of “1” to the EPi_NULMD bit.
Note:
The M66291 is equipped with 3 Kbytes FIFO buffer. The Maximum buffer size is 1024Bytes for an endpoint, and
the minimum one is 64Bytes.
(5) EPi_DBLB (Double Buffer Mode) Bit (b7)
This bit sets the single buffer mode/double buffer mode.
This bit is applicable to bulk/isochronous/interrupt transfers (set by the EPi_TYP bits).
When set to double buffer mode, 2 buffers of size set by the EPi_Buf_siz bits are secured and are allocated to
SIE side buffer and CPU side buffer.
Double buffer mode when set to OUT buffer (EPi_DIR bit = “0”)
SIE side buffer:
The data received by SIE can be written.
Can not be accessed by CPU/DMA.
CPU side buffer:
Can not be accessed by SIE.
The received data can be read by CPU/DMA.
Buffer toggle condition (switching of SIE side buffer and CPU side buffer)
SIE side buffer receive completion and CPU side buffer read completion (empty)
The receive completion changes according to the single/continuous transmit/receive mode.
For details, refer to the “EPi_RWMD bit” and the “TGL bit”.
Double buffer mode when set to IN buffer (EPi_DIR bit = “1”)
SIE side buffer:
SIE can transmit the written data.
Can not be accessed by CPU/DMA.
CPU side buffer:
Can not be accessed by SIE.
CPU/DMA can write the data for transmission.
Buffer toggle condition (switching of SIE side buffer and CPU side buffer)
CPU side buffer write completion and SIE side buffer transmit completion (empty)
The write and transmit completion changes according to the single/continuous
transmit/receive mode.
For details, refer to the “EPi_RWMD bit”.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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