- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98008 > M66291GP UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號(hào)： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 56/128頁(yè) |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
M66291GP/HP
Rev 1.01 2004.11.01 page 31 of 122
(5) CTRT (Control Transfer Stage Transition Interrupt) Bit (b11)
This bit indicates the transition of stage in control transfers.
This bit is set to “1” when the stage transition of control transfer takes place as follows (control transfer stage
transition interrupt occurs):
Refer to Figure 2.7.
Setup Stage Complete (When transmitting ACK)
Control Write Transfer Status Stage Transition (When receiving IN token)
Control Read Transfer Status Stage Transition (When receiving OUT token)
Control Transfer Complete (When transmitting or receiving ACK)
Control Transfer Sequence Error (When error occurs)
The Conditions that this bit indicates "1" depend on the WDST, RDST, CMPL or SERR bits.
This bit is cleared to “0” by writing “0” (interrupt is cleared).
The present stage can be confirmed by the CTSQ bits.
(6) BEMP (Buffer Empty/Size Over Error Interrupt) Bit (b10)
This bit indicates the occurrence of “buffer empty” or “buffer size over error”.
This bit is set to “1” when the EPB_EMP_OVR bit is set to “1” (buffer empty/buffer size over error interrupt
occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 3 to “0”.
For details, refer to “Interrupt Status Register 3”.
(7) INTN (Buffer Not Ready Interrupt) Bit (b9)
This bit indicates the NAK has been sent to the host because of the “buffer not ready” state.
This bit is set to “1” when the EPB_NRDY bit is set to “1” (buffer not ready interrupt occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 2 to “0”.
For details, refer to “Interrupt Status Register 2”.
(8) INTR (Buffer Ready Interrupt) Bit (b8)
This bit indicates the “buffer ready” state (that can be read/written).
This bit is set to “1” when the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 1 to “0”.
For details, refer to “Interrupt Status Register 1”.
(9) Vbus (Vbus Level) Bit (b7)
This bit indicates the state of Vbus pin.
When this bit changes, the VBUS bit is set to “1”.
This bit is capable of reading the correct value even if the clock is not supplied (Note).
Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.
(10) DVSQ (Device State) Bits (b6~b4)
These bits indicate the present device states as follows:
000 : Powered State
Power ON state
001 : Default State
USB bus reset detected state
010 : Address State
SET_ADDRESS request executed state
011 : Configured State
SET_CONFIGURATION request executed state
1xx : Suspended State
“suspended” detected state
Depending on the changes of these device states, the DVST bit and the RESM bit are set to “1” (set
enable/disable by the URST, SADR, SCFG or SUSP bits). For details, refer to “DVST bit” and Figure 2.6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC08AZ0 | 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQFP100 |
| M69030 | GRAPHICS PROCESSOR, PBGA278 |
| MA4T85633 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| MA4T85600 | Si, RF POWER TRANSISTOR |
| MA4T85635 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。