參數(shù)資料
型號(hào): M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 70/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 44 of 122
2.21 EP0 Packet Size Register
EP0 Packet Size Register (EP0_PACKET_SIZE)
<Address : H’2A>
b15
14
13
12
11
10
9876
54321
b0
EP0_MXPS
0
00
001000
-
--
------
-
------
<H/W reset : H'0008>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15~7
Reserved. Set it to “0”.
00
6~0
EP0_MXPS
Maximum Packet Size
Upper limit of the transmit/receive data for one packet transfer
(Settable only 8,16,32 and 64)
(1) EP0_MXPS (Maximum Packet Size) Bits (b6~b0)
These bits set the upper limit (byte count) of the transmit/receive data for one packet transfer at data stage.
Set the value of bMaxPacketSize0 transmitted to the host.
At the time of transmitting, the data equivalent to the size set by these bits is read from the buffer for
transmission. In case the buffer does not have the data equivalent to the size set by these bits, the data is
transmitted as the short packet.
At the time of receiving, the data equivalent to the size set by these bits is written to the buffer. If the received
packet data is larger than the size set by these bits, the following bits are set to "1":
The EPB_EMP_OVR bit.
(buffer empty/Size over error interrupt occurs when the EPB_EMPE bit is set to “1”.)
The CTRT bit when the SERR bit is set to “1”.
(control transfer stage transition interrupt occurs.)
Note:
Set these bits after setting the response PID to NAK (EP0_PID bits = “00”).
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