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參數(shù)資料
| 型號(hào)： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 47/128頁(yè) |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 23 of 122
(1) VBSE (Vbus Interrupt Enable) Bit (b15)
This bit sets enable/disable of Vbus interrupt.
When this bit is set to “1”, the interrupt occurs if VBUS bit is set to “1”.
This bit is capable of writing/reading even if the clock is not supplied (Note).
Note :
At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.
(2) RSME (Resume Interrupt Enable) Bit (b14)
This bit sets enable/disable of resume interrupt.
When this bit is set to “1”, the interrupt occurs if RESM bit is set to “1”.
This bit is capable of writing/reading even if the clock is not supplied (Note).
Note :
At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.
(3) SOFE (SOF Detect Interrupt Enable) Bit (b13)
This bit sets enable/disable of SOF detect interrupt.
When this bit is set to “1”, the interrupt occurs if SOFR bit is set to “1”.
(4) DVSE (Device State Transition Interrupt Enable) Bit (b12)
This bit sets enable/disable of device state transition interrupt.
When this bit is set to “1”, the interrupt occurs if DVST bit is set to “1”.
The Conditions the DVST bit set are depend on the URST, SADR, SCFG or SUSP.
(5) CTRE (Control Transfer Transition Interrupt Enable) Bit (b11)
This bit sets enable/disable of control transfer transition interrupt.
When this bit is set to “1”, the interrupt occurs if CTRT bit is set to “1”.
The Conditions the DVST bit set are depend on the WDST, RDST, CMPL or SERR.
The complete of setup stage can not set enable/disable to set CTRT bit to “1”.
(6) BEMPE (Buffer Empty/Size Over Error Interrupt Enable) Bit (b10)
This bit sets enable/disable of buffer empty/size over error interrupt.
When this bit is set to “1”, the interrupt occurs if BEMP bit is set to “1”.
(7) INTNE (Buffer Not Ready Interrupt Enable) Bit (b9)
This bit sets enable/disable of buffer not ready interrupt.
When this bit is set to “1”, the interrupt occurs if INTN bit is set to “1”.
(8) INTRE (Buffer Ready Interrupt Enable) Bit (b8)
This bit sets enable/disable of buffer ready interrupt.
When this bit is set to “1”, the interrupt occurs if INTR bit is set to “1”.
(9) URST (USB Reset Detect) Bit (b7)
This bit selects whether to set the DVST bit to “1” or not at the USB bus reset detection.
The register is initialized by the USB reset detection, irrespective of the value of this bit.
(10) SADR (SET_ADDRESS Execute) Bit (b6)
This bit selects whether to set the DVST bit to “1” or not at the SET_ADDRESS execution.
For details, refer to “DVST bit”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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