參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 3/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 98 of 122
3.5.1
FIFO Buffer Management
The M66291 is equipped with the registers below in order to execute high-level management of the FIFO
buffer set to continuous transmit/receive mode.
(1) SIE_FIFO Status Register
This register can forcibly toggle the FIFO buffer at SIE side of double buffer, enabling the CPU to access to
the SIE side FIFO. Further, the CPU can refer to the received data number in the SIE side FIFO.
(2) Transaction Count Register
When the continuous transfer mode buffer set in the OUT bulk transfer, the data receive count by MAX
packet size is specified, enabling the transaction only for the set count. It is convenient for the DMA
transfer.
(3) FIFO Status Register
This register is used for referring to the FIFO buffer status.
3.5.2
Cautions at FIFO Data Access
Make sure of the items as follows when accessing the FIFO Data Register.
When 8-bit width is selected in CPU interface:
The FIFO data can not be set to 16-bit mode by the register bit (Octl), while *LWR pin becomes valid as the
write strobe at 8-bit mode.
When 16-bit width is selected in CPU interface:
The FIFO data can be set both to 16-bit and 8-bit modes by the register bit (Octl).
B-1) 16-bit mode (Octl bit =“0”)
When accessing data for write, assert *HWR and *LWR pins simultaneously for word access, and *LWR
pin for byte access. At byte access, D7 to 0 become valid.
B-2) 8-bit mode (Octl bit =“1”)
When accessing data for write, *LWR pin is valid as the write strobe. Here, D7 to 0 become valid.
When accessing data for read, D15 to 8 and D7 to 0 are the same.
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