參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 54/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 29 of 122
b
Bit name
Function
R
W
7
Vbus
Vbus Level
Read
0 :
"L"
1 :
"H"
Write
Invalid (Ignored when written)
×
6~4
DVSQ
Device State
Read
000 : Powered state
001 : Default state
010 : Address state
011 : Configured state
1xx : Suspended state (Note)
Write
Invalid (Ignored when written)
×
3
VALID
Setup Packet Detect
Read
0 :
No detection
1 :
Receiving the setup packet
Write
0 :
This VALID bit clear
1 :
Invalid (Ignored when written)
2~0
CTSQ
Control Transfer Stage
Read
000 : Idle or setup stage
001 : Control read transfer data stage
010 : Control read transfer status stage
011 : Control write transfer data stage
100 : Control write transfer status stage
101 : Control write no data transfer status stage
110 : Control transfer sequence error
111 : Reserved
Write
Invalid (Ignored when written)
×
Note : x is a optional value.
The b15 to b8 of this register are interrupt status bits. When the bit of the Interrupt Enable Register
corresponding to these bits are set to “1” (interrupt enable), the interrupt occurs by setting these bits to “1”.
(1) VBUS (Vbus Interrupt) Bit (b15)
This bit indicates the change of Vbus input.
This bit is set to “1” (Vbus interrupt occurs) when the Vbus input changes (“L”->“H” or “H”->“L”).
This bit is cleared to “0” by writing “0” (interrupt is cleared).
This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by
writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will
be accepted).
Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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