參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 2/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 8 of 122
Item
Pin Name
Input/
Output
Function
Pin
Count
*Dack1
(Note1)
Input
DMA Acknowledge 1
This pin enables access of FIFO by DMA transfer for DMA channel 1.
1
DMA
interface
*TC1
Input
Terminal Count 1
This pin indicates the final transfer cycle at “L” level for DMA channel 1.
This is valid only in write cycle. Set to “H” level when not used.
1
D+
Input/
Output
USB Data (+)
D+ of USB. Connect an external resistance in series.
1
D-
Input/
Output
USB Data (-)
D- of USB. Connect an external resistance in series.
1
Vbus
Input
Vbus Input (with built-in pulldown resistance)
Connect to the Vbus of USB bus or to the 5V power supply.
Connection or shutdown of the Vbus can be detected.
1
USB
interface
TrON
Output
TrON Output
This pin is connected to the D+ pullup resistance of 1.5 K
.
This pin is used to control ON/OFF of the pullup resistance.
1
*RST
Input
Reset
This pin is used to initialize the values of the internal register or the counter at
"L" level.
1
Xin
Input
Oscillator
Input
1
Xout
Output
Oscillator
Output
These pins are used to input/output the signals of internal clock
oscillation circuits. Connect a crystal unit between Xin and Xout
pins.
If an external clock signal is used, connect it to the Xin pin and
leave the Xout pin open.
1
TEST
Input
TEST Input (with built-in pulldown resistance)
This pin is input for the test. Set to "L" level or keep open.
1
CoreVcc
(Note 2)
Core Power Supply
These pins are used as the power source for internal logic, FIFO memory, PLL
circuit, USB transceiver and oscillation buffer.
2
IOVcc
(Note 3)
I/O Power Supply
2
Others
GND
Ground
3
A pin preceded by an asterisk "*" is an active low pin.
(Example: *CS pin is an active low, CS)
Note 1: The polarities of *Dreq, *Dack, *INT, and *SOF pins can be changed by the internal registers.
Note 2: The Xin, Xout, Vbus, D+ and D- pins are all driven by CoreVcc.
Note 3: The pins for bus interface, interrupt, DMA control, reset and test are all driven by IOVcc. See
Figure 1.2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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