- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98008 > M66291GP UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 78/128頁 |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當(dāng)前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
M66291GP/HP
Rev 1.01 2004.11.01 page 51 of 122
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Note:
In case the transmit data exists in the buffer for EP0_FIFO, the buffer empty interrupt occurs in the concerned
endpoint when “1” is written to the BCLR bit.
(4) E0req (EP0_FIFO Ready) Bit (b11)
When this bit is equal to “1”, this bit indicates the states as follows:
EP0_FIFO Data Register can not be accessed.
The IVAL bit value of this register is invalid.
The ODLN bit values of this register are invalid.
Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.
(5) CCPL (Control Transfer Control) Bit (b10)
This bit controls the status stage of the control transfer.
When this bit is set to “1”, the operations below are executed at status stage of the control transfer and notifies
the normal completion of the control transfer:
When set to control write transfer (ISEL bit = “0”)
Transmits the zero-length packet after receiving IN token if the EP0_PID bits are set to “01”.
When set to control read transfer (ISEL bit = “1”)
ACK response to the host after receiving the zero-length packet following OUT token if the
EP0_PID bits are set to “01”.
When this bit is set to “0”, NAK response is executed to the host after receiving the IN token/OUT token at
status stage of the control transfer.
This bit is automatically cleared to “0” by receiving the setup token.
(6) ODLN (Control Write Receive Data Length) Bits (b8~b0)
These bits are valid for control write transfer and indicate the data number (byte count) received from the
CPU side buffer.
Further, these bits are set to execute countdown when the EP0_FIFO Data Register is read out. This
operation changes according to the RCNT bit. For details, refer to “RCNT bit”.
These bits indicate the valid value when the E0req bit of this register is equal to “0”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC08AZ0 | 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQFP100 |
| M69030 | GRAPHICS PROCESSOR, PBGA278 |
| MA4T85633 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| MA4T85600 | Si, RF POWER TRANSISTOR |
| MA4T85635 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。