參數(shù)資料
型號： M66291GP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 71/128頁
文件大?。?/td> 928K
代理商： M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 45 of 122
2.22 Automatic Response Control Register
Automatic Response Control Register (AUTO_RESPONSE_CONTROL)
<Address : H’2C>
b15
14
13
12
11
10
9876
54321
b0
ASCN
ASAD
0
000
-
---
-
--
<H/W reset : H'0000>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15~2
Reserved. Set it to “0”.
00
1
ASCN
SET_CONFIGURATION Automatic Response
Mode
0 :
Invalid of automatic response mode for
SET_CONFIGURATION
1 :
Valid of automatic response mode for
SET_CONFIGURATION
0
ASAD
SET_ADDRESS Automatic Response Mode
0 :
Invalid of automatic response mode for SET_ADDRESS
1 :
Valid of automatic response mode for SET_ADDRESS
(1) ASCN (SET_CONFIGURATION Automatic Response Mode) Bit (b1)
This bit sets the valid/invalid of automatic response mode for SET_CONFIGURATION request.
With the automatic response mode set to valid, zero-length packet is automatically transmitted against the
requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”
(control transfer stage transition interrupt does not occur).
SET_CONFIGURATION request of Configuration Value ≠ 0 in Address state
SET_CONFIGURATION request of Configuration Value = 0 in Configured state
No automatic response is executed when the SET_CONFIGURATION request other than the ones given
above is received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).
When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SCFG bit is
set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).
(2) ASAD (SET_ADDRESS Automatic Response Mode) Bit (b0)
This bit sets the valid/invalid of automatic response mode for SET_ADDRESS request.
With the automatic response mode set to valid, zero-length packet is automatically transmitted against the
requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”
(control transfer stage transition interrupt does not occur).
SET_ADDRESS request at Default state
No automatic response is executed when the SET_ADDRESS request other than the ones given above is
received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).
When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SADR bit
is set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66291GP#201 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP
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M66291GPRB0S 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48
M66291HP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller)
M66291HP#200D 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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