參數資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數: 79/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 52 of 122
2.25 EP0_FIFO Data Register
EP0_FIFO Data Register (EP0_FIFO_DATA)
<Address : H’34>
b15
14
13
12
11
10
9876
54321
b0
EP0_FIFO
????
??????
?
?????
----
------
----
------
<H/W reset : H'????>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15~0
EP0_FIFO
EP0_FIFO Data
<When set to control write transfer>
Read
Reads receive data
<When set to control read transfer>
Write
Writes transmit data
Note:The upper 8 bits (b15 to b8) become invalid in the 8-bit-mode (using the Octl bit of the EP0_FIFO Select Register or
*HWR/*BYTE pin).
(1) EP0_FIFO (EP0_FIFO Data) Bits (b15~b0)
The receive data from the CPU side buffer is read or the transmit data to the CPU side buffer is written
through this register.
When set to control write transfer (ISEL bit = “0”), the receive data from the buffer is read through this
register.
When set to control read transfer (ISEL bit = “1”), the transmit data to the buffer is written through this
register.
Make sure that the E0req bit is set to “0” before reading/writing these bits.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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