參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 35/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 12 of 122
2.1 USB Operation Enable Register
USB Operation Enable Register (USB_ENABLE)
<Address : H’00>
b15
14
13
12
11
10
987
654321
b0
XCKE
PLLC
Xtal
SCKE USBPC
Tr_on
USBE
0
-
<H/W reset : H'0000>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15
XCKE
Oscillation Buffer Enable
0 :
Disable oscillation buffer (Disable clock supply to inside
PLL)
1 :
Enable oscillation buffer (Enable clock supply to inside
PLL)
14
PLLC
PLL Operation Enable
0 :
Disable PLL (PLL through)
1 :
Enable PLL
13~12
Xtal
Clock Select
00 : External clock frequency : 48 MHz (PLL through)
10 : External clock frequency : 24 MHz
01 : External clock frequency : 12 MHz
11 : External clock frequency : 6 MHz
11
SCKE
Internal Clock Enable
0 :
Disable Internal clock
1 :
Enable Internal clock
10
USBPC
USB Transceiver Power Control
0 :
Disable USB transceiver
1 :
Enable USB transceiver
9~8
Tr_on
Tr_on Output Control
00 : TrON output ="Hi-Z" (SIE operate stop)
01 : TrON output ="L"
10 : Reserved
11 : TrON output ="H"
7~1
Reserved. Set it to “0”.
00
0
USBE
USB Module Operation Enable
0 :
S/W reset state
1 :
S/W reset state release
.
(1) XCKE (Oscillation Buffer Enable) Bit (b15)
This bit sets enable/disable of the oscillation buffer.
The output clock from the oscillation buffer is supplied to the PLL.
Refer to Figure 2.3.
(2) PLLC (PLL Operation Enable) Bit (b14)
This bit sets enable/disable of PLL.
When this bit is set to “1”, the external clock into the PLL is multiplied according to the value set in the Xtal
bits before being output to the core block. Set the XCKE bit to “1” and wait until the oscillation circuit starts
and becomes stable before setting this bit to “1”.
When this bit is set to “0”, PLL stops operation and the external clock into the PLL is output to the core block
without being multiplied. Hence, be sure to supply the 48 MHz clock to the oscillation buffer when setting this
bit to “0”.
Refer to Figure 2.3.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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