參數(shù)資料
型號(hào)： M66291GP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 62/128頁
文件大?。?/td> 928K
代理商： M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 37 of 122
2.15 Interrupt Status Register 3
Interrupt Status Register 3 (INT_STATUS3)
<Address : H’1E>
b15
14
13
12
11
10
9876
54321
b0
EPB_EMP_OVR
0
00
-
<H/W reset : H'0000>
<S/W reset : H'0000>
<USB bus reset : ->
b
Bit name
Function
R
W
15~7
Reserved. Set it to “0”.
00
6~0
EPB_EMP_OVR
Buffer Empty/Size Over Interrupt
Read
0 :
No occurrence of interrupt
1 :
Occurrence of interrupt
Write
0 :
Clear interrupt
1 :
Invalid (Ignored when written)
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
corresponds to EP0.
(1) EPB_EMP_OVR (Buffer Empty/Size Over Interrupt) Bits (b6~b0)
These bits indicate that the received data size exceeds the maximum packet size or that the buffers of the
endpoints 0 to 6 are empty.
Endpoint 0
When set to control write transfer (ISEL bit = “0”)
The condition for this bit to be set to “1” is as follows:
Receives packet data with size exceeding the one set by the EP0 Packet Size Register
(Size-over detection).
In this case, the EP0_PID bits are set to STALL response.
Further the CTRT bit sets to “1” if the SERR bit is set to “1”.
This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.
When set to control read transfer (ISEL bit = “1”)
The condition for this bit to be set to “1” is as follows:
When the IVAL bit of the EP0_FIFO Control Register changes from “1” to “0”.
When transmit data exist in the buffer for EP0_FIFO and “1” is written to the BCLR bit.
Endpoint 1~6
When set to OUT buffer (EPi_DIR bit = “0”)
The condition for this bit to be set to “1” is as follows:
Receives packet data with size exceeding the one set by the EPi_MXPS bits
(Size-over detection).
The EPi_PID bits are set to STALL response.
This bit isn’t set to “1” at isochronous transfer.
This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.
When set to IN buffer (EPi_DIR bit = “1”)
The condition for this bit to be set to “1” is as follows:
When the data of SIE side buffer are all transmitted with the data not written to the CPU
side buffer (Buffer empty).
The conditions for this bit to be cleared to “0” in all bits are as follows:
Writes “0” to this bit.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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