
M66291GP/HP
Rev 1.01 2004.11.01 page 42 of 122
2.20 Control Transfer Control Register
Control Transfer Control Register (CONTROL_TRANSFER)
<Address : H’28>
b15
14
13
12
11
10
9876
54321
b0
CTRR
Ctr_Rd_Buf_Nmb
CTRW
Ctr_Wr_Buf_Nmb
0
000
00000
0
00000
-
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<H/W reset : H'0000>
<S/W reset :->
<USB bus reset : ->
b
Bit name
Function
R
W
15
CTRR
Control Read Transfer Continuous Transmit
Mode
0 :
Single transmit mode
1 :
Continuous transmit mode
14
Reserved. Set it to "0".
00
13~8
Ctr_Rd_Buf_Nmb
Control Read Buffer Start Number
The top block number for the Control Read buffer
7CTRW
Control Write Transfer Continuous Receive
Mode
0 :
Unit receive mode
1 :
Continuous receive mode
6
Reserved. Set it to “0”.
00
5~0
Ctr_Wr_Buf_Nmb
Control Write Buffer Start Number
The top block number for the Control Write buffer
(1) CTRR (Control Read Transfer Continuous Transmit Mode) Bit (b15)
This bit sets the transmit mode at data stage of the control read transfer.
In case of single transmit mode, the transmit completes after transmitting one packet under the condition as
follows:
Transmits the data equivalent to the size set by the EP0 Packet Size Register or transmits a short
packet by setting the IVAL bit to “1”.
In case of continuous transmit mode, the transmit completes after transmitting several packets under the
condition as follows:
Transmits the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length
Register or transmits a short packet by setting the IVAL bit to “1”.
In case of single transmit mode, the writing completes under the conditions as follows:
Writes the data equivalent to the size set by the EP0 Packet Size Register to the buffer
(The IVAL bit of the EP0_FIFO Control Register changed to “1”).
Writes “1” to the IVAL bit of the EP0_FIFO Control Register.
In case of continuous transmit mode, the writing completes under the conditions as follows:
Writes the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length
Register (The IVAL bit of the EP0_FIFO Control Register changed to “1”).
Writes “1” to the IVAL bit of the EP0_FIFO Control Register.
The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.
(2) Ctr_Rd_Buf_Nmb (Control Read Buffer Start Number) Bits (b13~b8)
These bits set the beginning block number of the buffer to be used in control read transfer. The block number
is a number by dividing the FIFO buffer into 64 byte sections (Note 1).
When the mode is set to single transmit (CTRR bit = “0”), the blocks set by these bits only are used and, from
the following block, it is possible to set to the buffer of a different endpoint.
When the mode is set to continuous transmit (CTRR bit = “1”), the buffer equivalent to the size set by the
EP0_FIFO Continuous Transmit Data Length Register (max. 256 bytes) is used from the block numbers set by
these bits (Note 2).
Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H’0 to H’2F.
Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.