參數(shù)資料
型號(hào): M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 97/128頁
文件大?。?/td> 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 68 of 122
(3) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)
This bit indicates valid value when the Dreq bit of this register is equal to “0”.
The operation of this bit is the same as that of the IVAL bit of the CPU_FIFO Control Register.
Take care the setting of the EPB_RDY bit to “1” using this bit (buffer ready interrupt occurs) changes
according to the INTM bit (Refer to “EPB_RDY/INTM bit”).
(4) BCLR (Buffer Clear) Bit (b12)
This bit indicates valid value when the Dreq bit of this register is set to “0”.
The operation of this bit is the same as that of the BCLR bit of the CPU_FIFO Control Register.
(5) Dreq (D_FIFO Ready) Bit (b11)
When this bit is equal to “1”, this bit indicates the states as follows:
Dn_FIFO Data Register can not be accessed.
The IVAL bit value of this register is invalid.
The DMA_DTLN bit values of this register are invalid.
Make sure that this bit is equal to “0” before making access to the aforesaid registers/bits.
(6) DMA_DTLN (D_FIFO Receive Data Length Register) Bits (b10~b0)
These bits are valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and indicates the receive
data number (byte count) in the CPU side buffer.
These bits indicate the valid value when the Dreq bit of this register is equal to “0”.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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