參數(shù)資料
型號： M30L0T8000B0ZAQE
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88
文件頁數(shù)： 88/103頁
文件大?。?/td> 794K
代理商： M30L0T8000B0ZAQE
M30L0T8000T0, M30L0T8000B0
Common Flash Interface
85/103
1.
The variable P is a pointer which is defined at CFI offset 015h.
2.
Bank Regions. There are two Bank Regions, see Tables 30 to 35 in Appendix A.
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 1):Page
mode and Synchronous mode capabilities
(defined in Table 42)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+40)h = 14Ah
03h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks in each bank
Bits 16-31: n×256 = number of bytes in erase
block region
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h =14Eh
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+45)h = 14Fh
00h
(P+46)h = 150h
02h
Bank Region 2 (Erase Block Type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 2): Page
mode and Synchronous mode capabilities
(defined in Table 42)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
Table 45.
Bank and Erase Block Region 2 Information (continued)
M30L0T8000T0
M30L0T8000B0
Description
Offset
Data
Offset
Data
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