參數(shù)資料
型號(hào)： M30L0T8000B0ZAQE
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88
文件頁(yè)數(shù)： 11/103頁(yè)
文件大?。?/td> 794K
代理商： M30L0T8000B0ZAQE
M30L0T8000T0, M30L0T8000B0
Bus operations
15/103
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus Operations, for
a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See Figures 9, 10, and 11 Read AC Waveforms, and Tables
23 and 24 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated when Chip Enable and Write Enable are at
VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the
rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also
be latched prior to the write operation by toggling Latch Enable. In this case the Latch
Enable should be tied to VIH during the bus write operation.
See Figures 14 and 15, Write AC Waveforms, and Tables 25 and 26, Write AC
Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
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