參數(shù)資料
型號(hào)： M30L0T8000B0ZAQE
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88
文件頁(yè)數(shù)： 12/103頁(yè)
文件大小： 794K
代理商： M30L0T8000B0ZAQE
Bus operations
M30L0T8000T0, M30L0T8000B0
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the
Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory
content is no longer valid.
1.
X = Don't care.
2.
L can be tied to VIH if the valid address has been previously latched.
3.
Depends on G.
4.
WAIT signal polarity is configured using the Set Configuration Register command.
Table 3.
Bus Operations
Operation
E
G
W
L
RP
WAIT(4)
DQ15-DQ0
Bus Read
VIL
VIH
VIL
(2)
VIH
Data Output
Bus Write
VIL
VIH
VIL
(2)
VIH
Data Input
Address Latch
VIL
XVIH
VIL
VIH
Data Output or Hi-Z (3)
Output Disable
VIL
VIH
XVIH
Hi-Z
Standby
VIH
XX
X
VIH
Hi-Z
Reset
XXX
X
VIL
Hi-Z
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