參數(shù)資料
型號： M30L0T8000B0ZAQE
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88
文件頁數(shù)： 36/103頁
文件大小： 794K
代理商： M30L0T8000B0ZAQE
Configuration Register
M30L0T8000T0, M30L0T8000B0
6.4
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either
one or two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.
The Data Output Configuration must be configured using the following condition:
●
tK > tKQV + tQVK_CPU
where
●
tK is the clock period
●
tQVK_CPU is the data setup time required by the system CPU
●
tKQV is the clock to data valid time.
If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two
6.5
Wait Configuration Bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in
Synchronous Burst Read mode.
When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the
WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is
asserted one data cycle before the WAIT state.
6.6
Burst Type Bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst
Reads.
The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses
only.
See Table 12: Burst Type Definition, for the sequence of addresses output from a given
starting address in sequential mode.
6.7
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling
edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the
rising edge of the Clock is the active edge.
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