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參數(shù)資料
| 型號： | M30L0T8000B0ZAQE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88 |
| 封裝： | 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88 |
| 文件頁數(shù)： | 82/103頁 |
| 文件大?。?/td> | 794K |
| 代理商： | M30L0T8000B0ZAQE |
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Summary description
M30L0T8000T0, M30L0T8000B0
1
Summary description
The M30L0T8000T0 and M30L0T8000B0 are 256 Mbit (16 Mbit x16) non-volatile Flash
memories that may be erased electrically at block level and programmed in-system on a
Word-by-Word basis using a 1.7V to 2.0V VDD supply for the circuitry and a 2.2V to 3.6V
VDDQ supply for the Input/Output pins. An optional 9V VPP power supply is provided to
speed up factory programming.
The device features an asymmetrical block architecture and is based on a multi-level cell
technology.
The M30L0T8000T0/B0 has an array of 259 blocks, and is divided into 16 Mbit banks. There
are 15 banks each containing 16 main blocks of 64 KWords, and one parameter bank
containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in
one bank, read operations are possible in other banks. Only one bank at a time is allowed to
be in program or erase mode. It is possible to perform burst reads that cross bank
boundaries. The bank architecture is summarized in Table 2, and the memory maps are
shown in Figure 3 The Parameter Blocks are located at the top of the memory address
space for the M30L0T8000T0, and at the bottom for the M30L0T8000B0.
Each block can be erased separately. Erase can be suspended, in order to perform a
program or read operation in any other block, and then resumed. Program can be
suspended to read data at any memory location except for the one being programmed, and
then resumed. Each block can be programmed and erased over 100,000 cycles using the
supply voltage VDD. There is a Buffer Enhanced Factory programming command available
to speed up programming.
Program and erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports Synchronous Burst Read and Asynchronous Read from all blocks of
the memory array; at power-up the device is configured for Asynchronous Read. In
Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to
52MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
The M30L0T8000T0/B0 features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤VPPLK all blocks are protected against
program or erase. All blocks are locked at power- up.
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64
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