![](http://datasheet.mmic.net.cn/120000/M30833MJFP_datasheet_3558608/M30833MJFP_174.png)
Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Serial I/O
173
UARTi transmit/receive control register 1 (i=0 to 4)
Symbol
Address
When reset
UiC1(i=0 to 4)
036D16, 02ED16, 033D16, 032D16, 02FD16
0216
RW
RI
UiIRS
UiRRM
UiLCH
TE
RE
TI
Transmit
enable bit
Transmit buffer
empty flag
Receive
enable bit
Receive
complete flag
Clock divide
synchronizing stop bit
/error signal output
enable bit
SCLKSTPB
/UiERE
UARTi transmit
interrupt cause
select bit
UARTi
continuous
receive mode
enable bit
Data logic
select bit
0: Transmission disabled
1: Transmission enabled
0: Data present in transmit buffer register
1: No data present in transmit buffer register
0: Reception disabled
1: Reception enabled
0: Data present in receive buffer register
1: No data present in receive buffer register
0: Transmit buffer empty (TI = 1)
1: Transmit is completed (TXEPT = 1)
Set to "0"
0: Continuous receive
mode disabled
1: Continuous receive
mode enabled
0: No reverse
1: Reverse
Clock divide synchronizing stop bit
0: Synchronizing stop
1: Synchronous start (Note)
Note :When this bit and bit 7 of UARTi special mode register 2 are set, clock synchronizing function is used.
Bit name
Bit
symbol
Function
(Clock synchronous
serial I/O mode)
Function
(UART mode)
Set to "0"
b7
b6
b5
b4
b3
b2
b1
b0
UARTi special mode register (i=0 to 4)
Symbol
Address
When reset
UiSMR(i=0 to 4)
036716, 02E716, 033716, 032716, 02F716
0016
RW
LSYN
ABSCS
ACSE
SSS
IICM
BBS
ABC
0: Normal mode
1: IIC mode
0: Update per bit
1: Update per byte
0: STOP condition
detected
1: START condition
detected
0: Disabled
1: Enabled
Set to "0"
0: Ordinary
1: Falling edge of RxDi
0: Rising edge of transfer clock
1: Underflow signal of timer Ai
(Note 2)
Bit name
Bit
symbol
Function
(Clock synchronous
serial I/O mode)
Function
(UART mode)
IIC mode
select bit
Bus busy flag
Note 1: Nothing but "0" may be written.
Note 2: UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal,
UART3: timer A3 underflow signal, UART4: timer A4 underflow signal.
Note 3: When this bit and bit 7 of UARTi transmit/receive control register 1 are set, clock synchronizing
function is used.
Auto clear function
select bit of transmit
enable bit
SCLL sync
output enable
bit
Arbitration lost
detecting flag
control bit
Bus collision
detect sampling
clock select bit
Transmit start
condition
select bit
0: No auto clear function
1: Auto clear at
occurrence of bus
(Note 1)
SCLKDIV
Clock divide
set bit
0: No divided
1: Divided-by-2
(Note 3)
b7
b6
b5
b4
b3
b2
b1
b0
Figure 1.17.5. Serial I/O-related registers (4)