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Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Intelligent I/O (Serial I/O)
272
Interrupt request
generation timing
(2) Clock asynchronous serial I/O mode (UART) (group 0 and 1)
Table 1.23.14 lists the specifications for the UART mode.
Table 1.23.14. Specifications of UART mode
Item
Specification
Transfer data format
Character bit (transfer data)
: 8 bits
Start bit
: 1 bit
Stop bit
: 1 bit or 2 bits selected
Transfer clock
When internal clock is selected (Generates the transmit/receive clock in the phase
delayed waveform output mode)
_ Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2
k : values set to WG register 0
_ Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : Change ch2 TM function to WG function
Detects falling edge of start bit
Changes to the WG mode when the time measurement interrupt arrives
When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
Transmit enable bit = “1”
Write data to transmit buffer
Reception start condition
To start reception, the following requirements must be met:
Receive enable bit = “1”
When transmitting
_ When transmit buffer is empty, transmit interrupt cause select bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
When receiving
_ When data is transferred to SI/O receive buffer register
Error detection
Overrun error
: This error occurs when the next data is ready before contents
of SI/O receive buffer register are read out
Framing error
: This error occurs when the number of stop bits set is not detected
Select function
Stop bit length
: Stop bit length can be selected as 1 bit or 2 bits
LSB first/MSB first selection :
Whether transmit/receive begins with bit 0 or bit 7 can be selected
Transmit/receive data polarity switching :
This function is reversing ISTxD port output and ISRxD port input. (All I/O data level
are reversed.)
Data transfer bit length
: Transmission data length can be set between 1 to 8 bits