Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Three-phase motor control timers’ functions
155
Three-phase motor control timers’ functions
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms.
Figures 1.16.1 through 1.16.5 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0 (Note 4)
Symbol
Address
When reset
INVC0
030816
0016
b7
b6
b5
b4
b3
b2 b1
b0
Effective interrupt output
polarity select bit
INV00
Bit symbol
Bit name
Description
RW
INV01
Effective interrupt output
specification bit
INV02
Mode select bit
INV04
Positive and negative
phases concurrent L output
disable function enable bit
INV07
Software trigger bit
INV06
Modulation mode select
bit
INV05
Positive and negative
phases concurrent L output
detect flag
INV03
Output control bit
0: A timer B2 interrupt occurs when the
timer A1 reload control signal is “1”.
1: A timer B2 interrupt occurs when the
timer A1 reload control signal is “0”.
0: Not specified.
1: Selected by the INV00 bit.
0: Normal mode
1: Three-phase PWM output mode
0: Output disabled
1: Output enabled
0: Feature disabled
1: Feature enabled
0: Not detected yet
1: Already detected
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
0: Ignored
1: Trigger generated
(Note 6)
(Note 7)
(Note 3)
(Note 8)
(Note 5)
(Note 2)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Set bit 1 of this register to “1” after setting timer B2 interrupt occurrences frequency set counter.
Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = “1”).
Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,
and the timer B2 interrupt frequency set circuit works.
For U, U, V, V, W and W output from P80, P81, and P72 through P75, setting of function select registers A, B and
C is required.
Note 5: No value other than “0” can be written.
Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the
three-phase buffer register to the three-phase output shift register is made only once in synchronization with the
transfer trigger signal after writing to the three-phase output buffer register.
Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger
signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is
made with respect to every transfer trigger.
Note 8: The value, when read, is “0”.
(Note 4)
Figure 1.16.1. Registers related to timers for three-phase motor control