Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Reset
31
(019816)
(019916
(019A16)
(019B16)
(019C16)
(019D16)
(019E16)
(019F16)
(01A016)
(01A116)
(01A216)
(01A316)
(01A616)
(01A716)
(01AB16)
(01AC16)
(01AD16)
(01AE16)
(01AF16)
(01B016)
(01B116)
(01B216)
(01B316)
(01B416)
(01B516)
(01B616)
(01B716)
(01B816)
(01B916)
(01BA16)
(01BB16)
(01BC16)
(01BD16)
(017316)
(017416)
(017816)
(017A16)
(017B16)
(017C16)
(017D16)
(017E16)
(017F16)
(018016)
(018116)
(018216)
(018316)
(018416)
(018516)
(018616)
(018716)
(018816)
(018916)
(018A16)
(018B16)
(018C16)
(018D16)
(018E16)
(018F16)
(019016)
(019116)
(019216)
(019316)
(019416)
(019516)
(019616)
(019716)
Input function select register
Group 3 SI/O communication mode register
Group 3 SI/O communication control register
Group 3 SI/O transmit buffer register
Group 3 SI/O receive buffer register
Group 3 waveform generate register 0
Group 3 waveform generate register 1
Group 3 waveform generate register 2
Group 3 waveform generate register 3
Group 3 waveform generate register 4
Group 3 waveform generate register 5
Group 3 waveform generate register 6
Group 3 waveform generate register 7
Group 3 waveform generate control register 0
Group 3 waveform generate control register 1
Group 3 waveform generate control register 2
Group 3 waveform generate control register 3
Group 3 waveform generate control register 4
Group 3 waveform generate control register 5
Group 3 waveform generate control register 6
Group 3 waveform generate control register 7
(215)
(216)
(217)
(218)
(219)
(220)
(221)
(222)
(223)
(224)
(225)
(226)
(227)
(228)
(229)
(230)
(231)
(232)
(233)
(234)
(235)
(236)
(237)
(238)
(239)
(240)
(241)
(242)
(243)
(244)
(245)
(246)
(247)
(248)
(249)
(250)
(251)
(252)
(253)
(254)
(255)
(256)
(257)
Group 3 waveform generate mask register 4
Group 3 waveform generate mask register 5
Group 3 waveform generate mask register 6
Group 3 waveform generate mask register 7
Group 3 base timer register
Group 3 base timer control register 0
Group 3 base timer control register 1
Group 3 function enable register
Group 3 RTP output buffer register
Group 3 high-speed HDLC
communication control register 1
Group 3 high-speed HDLC
communication control register
Group 3 high-speed HDLC
communication register
Group 3 high-speed HDLC transmit counter
Group 3 high-speed HDLC data
compare register 0
Group 3 high-speed HDLC data
mask register 0
Group 3 high-speed HDLC data
compare register 1
Group 3 high-speed HDLC data
mask register 1
Group 3 high-speed HDLC data
compare register 2
Group 3 high-speed HDLC data
mask register 2
Group 3 high-speed HDLC data
compare register 3
X XX 0 0 000
00 ?0 X ? ?0
00 XX 000 0
0XX0X0 0 0
Group 2 IEBus transmit interrupt
cause detect register
Group 2 IEBus receive interrupt
cause detect register
0016
??16
0016
??16
0016
??16
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
00XXXXX0
??16
Figure 1.4.3. Device's internal status after a reset is cleared (5/10)